JPS643054B2 - - Google Patents

Description

[Detailed Description of the Invention] This invention relates to a large-scale semiconductor integrated circuit device (LSI).
Gate array type that configures various logic circuits by using all pre-wiring processes in common, forming circuit components such as transistors and resistive elements on the main surface of the semiconductor substrate in advance, and changing only the wiring process. This invention relates to improvements to reduce power consumption in the output buffer circuits of master slice LSIs, particularly those having a plurality of output buffer circuits composed of emitter-coupled logic (ECL) circuits.

Figure 1 is a gate array type master slice LSI
FIG. 2 is a block diagram showing the general configuration of the device.

In the figure, 101 to 105 are semiconductor substrates 10
Master pattern forming regions 111 to 114 for internal gates are formed on the main surface of the semiconductor substrate 100 in parallel to the X direction and spaced apart from each other in the Y direction, and each gate has a plurality of gates arranged thereon. This is a master pattern forming area for an input buffer or an output buffer, which is formed along each side of the periphery and has a plurality of gates arranged therein.
These master pattern forming areas 101 to 10
5 and 111 to 114, circuit components such as transistors and resistive elements are formed in advance by using all pre-wiring processes in common, and various logic gates can be simultaneously created by changing only the wiring process. , and provide wiring between each gate to configure various logic circuits. Note that the wiring inside the gate is in the master pattern forming areas 101 to 105 and 111 to 11.
The wiring between the gates is formed on the master pattern forming areas 101 to 105 and 111 to 114.
It is applied on wiring areas other than the above.

FIG. 2 is an equivalent circuit diagram showing an example of an internal gate circuit and an output buffer circuit constructed of a conventional gate array type master slice LSI with an ECL circuit configuration.

In the figure, IG and OB surrounded by dashed lines are an internal gate circuit and an output buffer circuit, respectively. In this figure, the internal gate circuit IG is a three-input transistor having three input transistors Q ₁ , Q ₂ and Q ₃ .
An example will be shown in which the output buffer circuit OB has a NOR configuration and has a non-inverting output type having one input transistor _Q10 . Q ₄ is the reference transistor of the internal gate circuit IG to which the reference voltage V _BB is applied to the base, and Q ₅ is the emitter follower transistor of the internal gate circuit IG whose emitter is connected to the emitter follower resistance element R ₄ and whose emitter is the output. It is. R ₁ is the input transistor Q ₁ ,
A load resistance element commonly connected to the collectors of Q ₂ and Q ₃ , R ₂ a load resistance element connected to the collector of reference transistor Q ₄ , and R ₃ a load resistance element commonly connected to the collectors of reference transistors Q ₁ , Q ₂ , Q ₃ and refer This is a resistance element commonly connected to the emitter of the lens transistor _Q4 . In addition, Q ₄₀ and Q ₅₀ are the reference transistor and emitter follower transistor of the output buffer circuit OB, respectively, and R ₁₀ and R ₂₀ are the load resistance elements connected to the collectors of the input transistor Q ₁₀ and the reference transistor Q ₄₀ , respectively. , R ₃₀ is the input transistor
A resistive element commonly connected to the emitters of _Q10 and reference transistor _Q40 , and _R40 is an emitter follower resistive element of the output buffer circuit OB connected to the emitter of emitter follower transistor _Q50 . Note that this emitter follower resistance element _R40 may be added externally. Also,
I ₁ , I ₂ and I ₃ are input terminals of the internal gate circuit IG,
O ₁ is the output terminal of the internal gate circuit IG, and I ₁₀ and O ₁₀ are the input terminal and output terminal of the output buffer circuit OB, respectively. Collector side power supply voltage
V _CC is normally zero (grounded), and the emitter side power supply voltage
V _EE is a negative voltage. Here, the resistance elements R ₁ , R ₂ ,
R ₃ , R ₄ , R ₁₀ , R ₂₀ , R ₃₀ , R ₄₀ , transistor Q ₁ ,
Circuit components such as Q ₂ , Q ₃ , Q ₄ , Q ₅ , Q ₁₀ , Q ₄₀ , and Q ₅₀ are previously formed in the master pattern formation area, and various patterns can be created by changing only the wiring process. A desired logic circuit is constructed by configuring logic gates and providing wiring between each gate.

By the way, in a gate array type master slice LSI with a conventional ECL circuit configuration, in order to achieve as high speed and high integration as possible, the circuit configuration elements of the internal gate circuit IG are miniaturized and the circuit configuration is In addition to reducing the stray capacitance of the element, the operating current is also minimized to reduce power consumption. On the other hand, the output buffer circuit OB
In this case, a large load capacitance may be added depending on the output terminal _O10 , so in this case as well, the output buffer must be A low resistance terminating resistor element is connected to the output terminal O ₁₀ of the circuit OB.
It is necessary to add R _TT (not shown) and set the circuit current of the output buffer circuit OB to a large current value. Moreover, since the circuit currents of all output buffer circuits OB configured on the same semiconductor substrate are set to the same current value, the output buffer circuits
Power consumption in OB increases. In particular, when high integration is achieved and the number of output buffer circuits OB is large, the power consumption in the output buffer circuits OB increases significantly, and the semiconductor substrate allows for the power consumption in the output buffer circuits OB. Since the proportion of power consumption increases, the internal gate circuit
Power consumption in IG is reduced and internal gate circuit
The drawback was that the desired speed performance with IG could not be obtained.

This invention was made in view of the above-mentioned drawbacks, and has a circuit configuration in which at least two types of circuit current values can be set for each output buffer circuit, and when the external load capacity is large, the output buffer circuit is By operating the output buffer circuit at a low circuit current value when the external load capacity is small, the output buffer circuit can be operated at a low circuit current value while ensuring the desired speed performance and output level voltage in the output buffer circuit. An object of the present invention is to provide an LSI in which desired speed performance can be obtained in the internal gate circuit by reducing the power consumption in the internal gate circuit and increasing the power consumption in the internal gate circuit accordingly.

FIG. 3 is a circuit configuration diagram showing an output buffer circuit of an LSI according to an embodiment of the present invention, and FIG. 3A is a configuration diagram of elements constituting the output buffer circuit formed in advance in a master pattern forming area. ,
FIGS. 3B and 3C are diagrams showing an example of the configuration of an output buffer circuit in a non-inverting output mode.

In the figure, the same reference numerals as those of the conventional example shown in FIG. 2 indicate equivalent parts, and the explanation thereof will be omitted.
R ₁₁ and R ₁₂ are load resistance elements corresponding to the load resistance element R ₁₀ of the above conventional example, R ₂₁ and R ₂₂ are load resistance elements corresponding to the load resistance element R 20 of the above conventional example, and R ₃₁ and R ₃₂ are load resistance elements corresponding to the load resistance element R ₁₀ of the above conventional example. This is a resistance element corresponding to the resistance element _R30 of the conventional example. In addition, the transistor
Q ₁₀ and Q ₄₀ and resistance elements R ₁₁ , R ₁₂ , resistance elements
R ₂₁ , R ₂₂ and resistance elements R ₃₁ , R ₃₂ constitute a current switching circuit, and the emitter follower transistor
Q ₅₀ and the emitter follower resistance element R ₄₀ constitute an emitter follower circuit.

In the output buffer circuit of this embodiment, FIG.
As shown in FIG _. 2, in addition to _the resistive elements R ₁₀ , R ₂₀ and _{R 30} of _the conventional current switching circuit shown in FIG.
R ₃₁ and R ₃₂ are formed in advance in the master pattern forming area in correspondence with each other, and resistive elements R ₁₁ , R ₁₂ and resistive elements R ₂₁ , R are formed in accordance with the magnitude of the load capacitance added to the output terminal. ₂₂ and resistive element
By changing R ₃₁ and R ₃₂ to parallel connection and independent connection, respectively, and setting the resistance values of each resistance element constituting the current switching circuit, excluding the emitter follower circuit, in two ways, the current switching circuit described above can be It is configured so that the circuit current can be switched between two values: a high current value and a low current value.

As shown in FIG. 3B, when the load capacitance added to the output terminal O ₁₀ is large, the resistive element R ₁₁ ,
R ₁₂ , resistance elements R ₂₁ , R ₂₂ and resistance elements R ₃₁ , R ₃₂
An open-emitter output format is used in which each is connected in parallel, and a terminating resistor _RTT with a resistance value smaller than the resistor _R40 is externally added to the output terminal _O10 , and the emitter side power supply voltage is connected to the terminating resistor _RTT . By applying a termination voltage V _TT that is smaller in absolute value than V _EE , the circuit current in the output buffer circuit is set to a high current value, and sufficient driving capability is provided to achieve the desired output level. Voltage can be secured. Furthermore, as shown in FIG. 3C, when the load capacitance added to the output terminal O ₁₀ is small, the resistance elements R ₁₁ , R ₁₂ , resistance elements R ₂₁ , R ₂₂ and resistance elements R ₃₁ , R ₃₂ Connect each individually,
By connecting the emitter follower resistance element _R40 to the emitter of the emitter follower transistor _Q50 and setting the circuit current in the output buffer circuit to a low current value, power consumption in the output buffer circuit is reduced. can do. Note that the circuit current of the current switching circuits other than the emitter follower circuit depends on the resistance value of the resistor element commonly connected to the emitter of the input transistor _Q10 and the emitter of the reference transistor _Q40 . A resistive element so that the circuit current value can be set
It is necessary to select the resistance values of R ₃₁ and R ₃₂ . Also,
It is necessary to select the resistance values of the resistance elements R ₁₁ and R ₁₂ and the resistance elements R ₂₁ and R ₂₂ so that a predetermined output level voltage can be secured for each high and low circuit current value.

Figure 4 shows the emitter follower transistor _Q50 when two circuit configurations are adopted in this embodiment.
FIG. 3 is a diagram showing an example of the relationship between the emitter follower current and the output voltage.

In the figure, the horizontal axis shows the emitter follower current of the emitter follower transistor _Q50 , and the vertical axis shows its output voltage. Curves A and B shown by solid lines each take the open emitter output form shown in Figure 3B, and the termination resistance element _RTT is replaced by a resistance element.
The characteristic curves for high and low output levels are shown in the case of a high circuit current value where the resistance value of _R40 is set to 50 to 100Ω, and the termination voltage _VTT is set to _−2V , which is less than the absolute value of voltage VB. , the intersection point _H1 of these curves A and B with the voltage drop straight line C due to the termination resistance element _RTT starting from the -2V point on the vertical axis.
and H ₂ are the operating points corresponding to the high output level voltage and low output level voltage, respectively, in this case. Curves D and H shown by dashed-dotted lines respectively indicate the high output level and the high output level when the output terminal _O10 is terminated with the emitter follower resistor _R40 and the resistor circuit current value is set as shown in FIG. 3C. Characteristic curves for low output levels are shown, and the emitter follower resistance element whose starting point is the emitter side power supply voltage V _EE on the vertical axis of these curves D and E.
The intersections L ₁ and L ₂ with the voltage drop straight line due to R ₄₀ are the operating points corresponding to the high output level voltage and the low output level voltage, respectively, in this case.

As shown in FIG. 4, the emitter follower current dependence of the output voltage of the emitter follower transistor _Q50 depends on the circuit current value, and this dependence becomes larger as the circuit current value becomes smaller. However, when the circuit current value is set to a low value, a desired output voltage can be obtained by employing the emitter follower resistance element _R40 having a high resistance value. Also,
Low resistance element R _TT with open emitter output format
When terminating at , a desired output voltage can be obtained by setting a high circuit current value.

As described above, in this embodiment, the circuit configuration of the output buffer circuit is switched between a high circuit current value and a low circuit current value depending on the magnitude of the load capacitance added to the output terminal _O10 , thereby achieving the desired value. Speed performance and output level voltage can be ensured, and power consumption in the output buffer circuit can be reduced. In particular, when high integration is achieved and there are a large number of output buffer circuits, the power consumption in the output buffer circuits can be significantly reduced. It becomes possible to increase power and improve speed performance.

In this embodiment, when the load capacitance added to the output terminal is small, the output terminal is terminated with a high-resistance emitter follower resistor formed on the main surface of the semiconductor substrate of the LSI, and when the load capacitance is large, the output terminal is terminated with an open emitter follower resistor. We have described the case where the output is in the form of an open-emitter and is terminated externally with a terminating resistor element with a low resistance value. Even when the value is changed, the same effects as in this embodiment can be obtained. Also,
In this example, excluding the emitter follower circuit,
Two resistive elements are formed for each of the current switching circuits, and two circuit current values can be set. However, the present invention is not limited to this configuration. Any configuration is sufficient as long as it can set more than one resistance value and can set two or more circuit current values according to each resistance value, and even in this case, the same effect as this embodiment can be obtained. Furthermore,
In this embodiment, only the case of the output buffer circuit with one input type and non-inverting output type was described.
It may be an inverted output format or a multi-input format, and the same effect as this embodiment can be obtained.

As explained above, in the LSI of this invention,
In a gate array type master slice LSI consisting of an ECL circuit, the current switching circuit of the output buffer circuit and the emitter follower circuit can be set to at least two circuit configurations by changing only the wiring process. By switching the output buffer circuit between a high circuit current value and a low circuit current value depending on the magnitude of the current, the power consumption in the output buffer circuit is reduced while ensuring the desired speed performance and output level voltage. The power consumption of the internal gate circuit can be increased by the amount of this reduction in power consumption, and the speed performance can be improved.

[Brief explanation of drawings]

Figure 1 is a gate array type master slice LSI
Figure 2 is a block diagram showing the general configuration of
An equivalent circuit showing an example of an internal gate circuit and an output buffer circuit configured in a conventional gate array type master slice LSI with an ECL circuit configuration. FIG. 3 is a circuit configuration showing an output buffer circuit of an LSI according to an embodiment of the present invention. In the figures, FIG. 3A is a configuration diagram of the elements constituting the output buffer circuit previously formed in the master pattern forming area, and FIGS. 3B and C are the configuration of the output buffer circuit in the case of a non-inverting output mode. It is a figure which shows an example. Fourth
The figure is a diagram showing an example of the relationship between the emitter follower current and the output voltage of the emitter follower transistor when two circuit configurations are adopted in the above embodiment. In the figure, 100 is a semiconductor substrate, Q ₁₀ and
Q ₄₀ is the input transistor and reference transistor (circuit components of the current switching circuit), Q ₅₀ is the emitter follower transistor,
R ₁₁ , R ₁₂ , R ₂₁ and R ₂₂ are load resistance elements (circuit components of the current switching circuit), R ₃₁ and R ₃₂ are resistance elements (circuit components of the current switching circuit), R ₄₀
is the emitter follower resistance element, and _O10 is the output terminal. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] 1. Various logic circuits can be constructed by forming circuit components such as transistors and resistive elements on the main surface of a semiconductor substrate in advance, and changing only the wiring process that connects these circuit components. A gate array type master slice semiconductor integrated circuit device comprising a plurality of output buffer circuits each having a current switching circuit and an emitter follower circuit configured with an emitter-coupled logic circuit, wherein the current switching circuit and the emitter follower circuit have a plurality of output buffer circuits. A large-scale semiconductor integrated circuit, characterized in that the circuit can be configured in at least two ways by changing only the wiring process, and the circuit current value of the output buffer circuit can be changed in at least two ways. circuit device. 2 Form at least two of each resistance element constituting the current switching circuit in advance,
Claim 1, characterized in that the current value of the current switching circuit is changed in at least two ways by changing the connection of each of the resistance elements by changing only the wiring process. Large-scale semiconductor integrated circuit device. 3. The resistance value of the emitter follower resistance element connected to the emitter of the emitter follower transistor constituting the emitter follower circuit is changed depending on the magnitude of the load capacitance added to the output terminal of the output buffer circuit, and A large-scale semiconductor integrated circuit device according to claim 1 or 2, characterized in that the circuit current value is changed. 4. When a large load capacity is added to the output terminal of the output buffer circuit, set the circuit current of the current switching circuit to a high current value, adopt an open emitter output form, and connect the output terminal externally to a low resistance resistor. When a small load capacitance is added to the above output terminal, the circuit current of the current switching circuit is set to a low current value, and the emitter follower resistance element with a high resistance value formed on the same semiconductor substrate is connected to the above. 3. The large-scale semiconductor integrated circuit device according to claim 1, wherein the large-scale semiconductor integrated circuit device is connected to an output terminal.