JPS6351716A - Latch circuit - Google Patents

Abstract

PURPOSE:To the speed of a circuit operation by using a clock inverter with both-phase driving a clock signal to set gate delay as one gate delay per stage. CONSTITUTION:By inputting a high level to a positive phase clock input terminal 17, and a low level to a negative phase clock input terminal 18, an N-type transistor 9, and a P-type transistor 11 are energized, and an N-type transistor 10, and a P-type transistor 12 are cut off. As a result, N-type transistors 5 and 7, and P-type transistors 6 land 8 are separated, and the data of a positive phase data input terminal 13, and of a negative phase data input terminal 14, are latched, and the data are outputted respectively to a positive phase output terminal 15, and a negative phase output terminal 16. By inputting a signal of low level to the positive phase clock input terminal 17, and a signal of high level to the negative phase clock input terminal 18, the N-type transistor 9, and the P-type transistor 11 are cut off, and the N-type transistor 10 and the P-type transistor 12 are energized. As a result, N-type transistors 1 and 3, and the P-type transistors 2 and 4 are separated, and the data of the positive phase output terminal 15 and of the negative phase output terminal 16, are held.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a latch circuit, and more particularly to a static latch circuit in which gate delay per stage is reduced.

2. Description of the Related Art There are two types of latch circuits that have been used in the past: Sftik type and dynamic type. First, examples of static type latch circuits are shown in FIGS. 6-8. Both examples have a feedback circuit.

FIG. 6 shows a latch circuit using four two-person gates. The output of the NOR gate 61 to which the positive phase data, the input D I n and the positive phase tally clock φ are input is connected to the input of the NOR gate 63 . On the other hand, the output of the NOR gate 62 to which the negative phase data inputs DI, . . . and the positive phase clock φ are input is connected to the input of the NOR gate 64. noah gate 63
The output of the NOR gate 64 is connected to the other input of the NOR gate 64, and the output of the NOR gate 63 is connected to the other input of the NOR gate 64, thereby forming a cross-connection. The output of the NOR gate 63 is a positive phase output Q, and the output of the NOR gate 64 is a negative phase output Q.

The contents of the latch change according to changes in the input when the positive phase clock signal is low, and the input is latched when the positive phase clock signal φ is high.

Figure 7 shows the D-
This is an example of a latch. A transmission gate 71 to which the positive phase data input Dir+ is input is connected to an inverter 73. The output of this inverter 73 is feedback-connected to its own input via an inverter 74 and a transmission gate 72 connected in series. Transmission gates 71 and 72
Input clocks φ and φ having opposite phases to each other. The output of the inverter 73 becomes the positive phase output Q of this D-latch.

Since clock signals having opposite phases are input to the transmission gates 71 and 72, when the positive phase clock signal φ is high, the transmission gate 71 becomes conductive and the transmission gate 72 becomes non-conductive, so that the positive phase data input Dir+ The contents of the latch change due to the change in , and the data is obtained as the positive phase output Q. When the positive phase clock signal φ is low, the transmission gate 71 is non-conductive, the transmission gate 72 is conductive, and the contents of the latch are stored.

FIG. 8 is a D-latch using a clocked inverter. A clocked inverter 81 to which positive-phase data inputs DI, . . . is input is connected to an inverter 82 . The output of this inverter 82 is feedback connected to the input of an inverter 820 via a clocked impark 83. Clock signals having opposite phases are input to the clocked inverters 81 and 83.

The output of inverter 82 is the output Q of this D-latch.

The D-latch of FIG. 8 differs only in that a clocked inverter is used in place of the transmission gate of FIG.

The operation of this D-latch of FIG. 8 is therefore identical to that of the D-latch shown in FIG. 7, except that the output of this D-latch is Q.

As can be seen from their respective configurations, each of the three latch circuits described above is configured to generate two gate delays per -stage.

As a latch circuit for reducing the gate delay to one gate per stage, there is a dynamic type circuit shown in FIGS. 10 and 11.

FIG. 10 is an example of a D-latch constructed using a transmission gate. The latch consists of a transmission gate 101 and a capacitance 102 in parallel with ground at the output of the transmission gate 101. Data is stored by accumulating charge in a capacitance 1 (12) such as a gate capacitance.

FIG. 11 is an example in which a D-latch is constructed using a clocked inverter. This latch consists of a clocked inverter 111 and a capacitor 112 in parallel with ground at its output.

Data is stored by accumulating charge in the capacitance 112.

Problems to be Solved by the Invention It has been shown that there are two types of conventional latch circuits: a static type and a dynamic type, but both have the following drawbacks. For example, a static latch circuit has a structure in which at least two gate delays occur per -&, which has the drawback of lowering the maximum operating frequency and reducing the circuit operating speed. On the other hand, dynamic latch circuits only require one gate delay per stage, but because they use a memory method that temporarily stores charge in a capacitor, they cannot operate over a wide operating frequency range, especially at low frequencies. The problem is that it is difficult to do.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a static latch circuit that can increase the circuit operating speed by reducing the gate delay to one per stage.

Means for Solving the Problems The present invention for solving the above problems is a latch circuit driven by both positive and negative phase clock signals, where the positive phase clock signal is high and the negative phase clock is low. Sometimes, it is two inverters that latch the forward and reverse input data and output it inverted. When the positive phase clock is low and the negative phase clock is high, the two inverters are connected cross-wise, and the forward and reverse input data is output. This is a circuit that holds both outputs.

More specifically, the latch circuit of the present invention includes a first N-type transistor whose gates are connected to each other to form a positive phase data input terminal, and whose drains are connected to each other to form a negative phase output terminal; P-type transistors, their gates are connected to each other to form a negative-phase data input terminal, their drains are connected to each other to form a positive-phase output terminal, and their respective sources are connected to the source of the first N-type transistor and the first A second N-type transistor and a second P-type transistor connected to the source of the P-type transistor have gates connected to the positive-phase output terminal, and drains connected to the negative-phase output terminal. A third N-type transistor and a third P-type transistor have their gates both connected to the negative phase output terminal, their drains both connected to the positive phase output terminal, and their respective sources connected to the third N-type transistor. a fourth N-type transistor connected to the source and the source of the third P-type transistor; a drain connected to the source of the first N-type transistor; and a gate connected to the positive-phase clock input terminal. a fifth N-type transistor whose source is connected to the ground, and a third N-type transistor whose drain is connected to the source, whose gate is connected to the reverse phase clock input terminal, and whose source is connected to the ground. a sixth N-type transistor;
a fifth P-type transistor whose drain is connected to the source of the first P'1) transistor, whose gate is connected to the negative phase clock input terminal, and whose source is connected to the power supply terminal; and a third P-type transistor. a sixth P-type transistor having a drain connected to the source thereof, a gate connected to the positive phase clock input terminal, and a source connected to the power supply terminal.

The first to sixth N-type transistors and the first to sixth P-type transistors are preferably CMOS.

Operation As described above, the circuit of the present invention is driven by clock signals of positive and negative phases. The positive phase data input terminal is connected to the negative phase output terminal through a clocked inverter, and the negative phase data input terminal is connected to the positive phase output terminal through another clocked inverter.

Therefore, this latch circuit latches the data at the positive phase data input terminal and the negative phase data input terminal, and outputs the data to the negative phase output terminal and the positive phase output terminal, respectively.

The circuit of the present invention further includes two inverters connected across each other between a line connecting a positive phase data input terminal and a negative phase output terminal and a line connecting a negative phase data input terminal and a positive phase output terminal. There is. This part is used to hold the data of the positive phase output terminal.

As described above, the circuit of the present invention performs the operation of a latch circuit, and has only one gate delay stage.

Therefore, by using this latch circuit, the circuit operating speed can be improved.

Example The present invention will be described below with reference to the drawings.

The latch circuit of the present invention has a logical configuration equivalent to the circuit shown in FIG. The circuit shown in FIG. 2 is composed of four clocked inverters. Positive phase data input terminal 13
is connected to the clocked inverter 25. On the other hand, the negative phase data input terminal 14 is connected to a clocked inverter 26 . The output of the clocked inverter 25 is connected to the negative phase output terminal 16 and, via the clocked inverter 28, to the positive phase output terminal 15, which is connected to the output of the clocked inverter 26. In contrast,
The output of the clocked inverter 26 is connected to the positive phase output terminal 15.
It is also connected to the reverse phase output terminal 16 which is connected to the output of the clocked inverter 25 via the clock toy and inverter 27 . clocked inverter 2
5.26 and clocked inverters 27.28 are input with mutually inverted clock signals.

FIG. 9 is a diagram in which a clocked inverter is constructed of CuO2. P-type transistor 92 and N-type transistor 9
3 are connected gate to drain and drain to drain. The points where the gates are connected are connected to the positive phase data input terminal, and the points where the drains are connected are connected to the negative phase output terminal.

The source of the P-type transistor 92 is the P-type transistor 9
Connected to the drain of 1. This P-type transistor 9
The gate of No. 1 is connected to the reverse phase clock input terminal, and the source is connected to the power supply terminal. The source of N-type transistor 93 is connected to the drain of N-type transistor 94.

The gate of the N-type transistor 94 is connected to the positive phase clock input terminal, and the source is connected to the ground.

The operation of the clocked inverter will be explained below.

When a high signal is supplied to the positive phase clock input terminal, a low signal is supplied to the negative phase clock input terminal. Then, P-type transistor 91 and N-type transistor 94 become conductive at the same time, and P-type transistor 92 and N-type transistor 93 operate as a normal inverter. On the other hand, when a low signal is supplied to the positive phase clock input terminal, the P-type transistor 91 and the N-type transistor 9
4 becomes non-conductive at the same time. In this case, the negative phase output terminal becomes high impedance.

FIG. 3 is a diagram in which the circuit shown in FIG. 2 is redrawn using FIG. 9. The drains and gates of the N-type transistor 1 and the P-type transistor 2 are connected, and the respective connection points form a negative phase output terminal 16 and a positive phase data input terminal 13. The drains and gates of the N-type transistor 3 and the P-type transistor 4 are connected, and their respective connection points form a positive-phase output terminal 15 and a negative-phase data input terminal 14. The drains of the N-type transistor 5 and the P-type transistor 6 are connected to each other, and an opposite phase output terminal 16 is formed.
, the gates are connected to each other, and the positive phase output terminal 15
is connected to. The drains of the N-type transistor 7 and the P-type transistor 8 are connected to each other, and a positive phase output terminal 15 is connected.
, the gates are connected to each other, and the reverse phase output terminal 16
is connected to. The source of N-type transistor 1 is connected to the drain of N-type transistor 9. The gate of the N-type transistor 9 is connected to the positive phase clock input terminal 17, and the source is connected to the ground 20. The source of P-type transistor 2 is connected to the drain of P-type transistor 11. The gate of the P-type transistor 11 is connected to an anti-phase clock input terminal 18, and the source is connected to a power supply terminal 19. The source of the N-type transistor 3 is connected to the drain of the N-type transistor 10. The gate of the N-type transistor 22 is connected to the positive phase clock input terminal 17, and the source is connected to the ground 22.

The source of P-type transistor 4 is connected to the drain of P-type transistor 24. The gate of the P-type transistor 24 is connected to the anti-phase clock input terminal 18, and the source is connected to the power supply terminal 19. The source of N-type transistor 5 is connected to the drain of N-type transistor 21. N
The gate of the type transistor 21 is connected to the reverse phase clock input terminal 1.
8, the source is connected to ground 20. The source of P-type transistor 6 is connected to the drain of P-type transistor 23. The gate of the P-type transistor 23 is connected to the positive phase clock input terminal 17, and the source is connected to the power supply terminal 19.
It is connected to the. The source of N-type transistor 7 is connected to the drain of N-type transistor 10. The gate of the N-type transistor 10 is connected to the anti-phase clock input terminal 18, and the source is connected to the ground 20. The source of P-type transistor 8 is connected to the drain of P-type transistor 12. The gate of the P-type transistor 12 is connected to the positive phase tarlock input terminal 17, and the source is connected to the power supply terminal.

FIG. 1 shows an embodiment of the present invention, which has a simplified configuration of the circuit shown in FIG. In FIG. 1, N-type transistors 9.22 are grouped together to form one N-type transistor 9, N-type transistors 2L10 are grouped together to form one N-type transistor 10, and P-type transistors 11.24 are grouped together to form one N-type transistor 10. The P-type transistors 12 and 23 are combined to form one P-type transistor 12.

This is because the sources of N-type transistors 9 and 21, N-type transistor 21 and 1O1P-type transistors 11 and 24, and P-type transistors 23 and 12 are connected to each other.
Moreover, since the gates are also connected to each other, the drain potentials of the transistors in each set are always equal. Therefore, even if two transistors are replaced with one transistor as described above, the logic will not change.

Furthermore, a comparison between FIG. 1 and FIG. 3 will be made. In FIG. 3, the positive-phase clock input terminal 17 is connected to the gates of the N-type transistor 9.22 and the P-type transistor 12.23, and the negative-phase clock input terminal 18 is connected to the gates of the N-type transistor 12.23.
．． 21 and the gates of P-type transistors 11 and 24. On the other hand, in FIG. 1, the positive phase clock input terminal 17 is connected to the gates of the N type transistor 9 and the P type transistor 12, and the negative phase clock input terminal 18 is connected to the gates of the N type transistor 10 and the P type transistor 11. It is connected to the.

In this way, in Figure 3, one clock input terminal has four
The gates of two transistors are connected, whereas the gates of two transistors are connected.
In the figure, only the gates of two transistors are connected to one clock input terminal. Therefore, the driving capacity of the logic circuit connected to the preceding stage may be half that of the circuit of FIG. 3 in the circuit of the present invention.

Next, referring to FIGS. 4 and 5, it will be explained that the circuit of the present invention shown in FIG. 1 functions as a latch.

FIG. 4 is a circuit diagram when a high signal is input to the positive phase clock input terminal 17 and a low signal is input to the negative phase clock input terminal 18 in FIG. When such a signal is input, N
type transistor 9 and P type transistor 11 are conductive, and N
P-type transistor 10 and P-type transistor 12 become non-conductive. As a result, the N-type transistor 5.7 and the P-type transistor 6.8 are separated, so that the circuit shown in FIG. 4 is obtained.

This circuit latches the data of the positive phase data input terminal 13 and the negative phase data input terminal 14, and outputs the data to the positive phase output terminal 1, respectively.
This circuit outputs data to an output terminal 16 having a phase opposite to that of the output terminal 5.

FIG. 5 shows the positive phase clock input terminal and terminal 17 in FIG.
7 is a circuit diagram when a low signal is input to the reverse phase clock input terminal 18 and a high signal is input to the reverse phase clock input terminal 18. FIG. When such a signal is input, N-type transistor 9 and P-type transistor 11 become non-conductive, and N-type transistor 10 and P-type transistor 12 become conductive. As a result, the N-type transistor 1.3 and the P-type transistor 2.4 are separated, so that the circuit shown in FIG. 5 is obtained.

This circuit consists of an N-type transistor 5 and a P-type transistor 6.
It has a configuration in which one inverter consisting of an N-type transistor 7 and a P-type transistor 8 are placed side by side. Therefore, it has the function of holding data at the positive phase output terminal 15 and the negative phase output terminal 16.

In the latch circuit shown in Figure 1, the gate delay per stage is equivalent to one clocked inverter stage, so this latch circuit can be divided into two stages.
By preparing a master-slave flip-flop, a static flip-flop whose gate delay is equivalent to one clocked inverter stage can be obtained.

As described in detail, the latch circuit of the present invention uses a clocked inverter with clocked signals driven in both phases, thereby realizing a static flip circuit with a gate delay equivalent to one stage of a clocked inverter. As a result, it is possible to improve the circuit operating speed.

Furthermore, by allowing the clocked inverters to share the gate to which the clock is input, the driving capacity of the preceding logic circuit can be reduced to half. As a result, it is possible to achieve low power consumption or miniaturization of the circuit.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the latch circuit of the present invention, FIG. 2 is a diagram showing the logical configuration of the latch circuit of the present invention, and FIG. 3 is a diagram showing the logical configuration of the latch circuit of the present invention. This is a circuit diagram composed of CMO3. FIG. 4 is a diagram of the circuit of the present invention shown in FIG. 1 when a high signal is input to the positive phase input data terminal and a low signal is input to the negative phase data input terminal. 5 is a diagram of the circuit of the present invention shown in FIG. 1 when a low signal is input to the positive phase input data terminal and a high signal is input to the negative phase input data terminal.
8 are conventional static latch circuits, FIG. 9 is a circuit diagram in which a clocked inverter is constructed of CMO3, and FIGS. 10 and 11 are conventional dynamic latch circuits. (Main reference numbers) 1, 3. 5.7.9.10.21.22.93.94
...N-type transistor, 2, 4. 6.8.11. ．． 12.23.24.91.
92... P-type transistor, 13... Positive phase data input terminal, 14... Negative phase data input terminal, 15... Positive phase output terminal, 16... Negative phase output terminal, 17
... Positive phase clock input terminal, 18... Negative phase clock input terminal, 19... Power supply terminal, 20... Ground, 25, 26
．． 27.28.81.83.111...Clocked in Park,

Claims (1)

[Claims] (1) A latch circuit driven by both positive and negative phase clock signals, which latches the positive and negative input data and outputs the inverted output when the positive phase clock signal is high and the negative phase clock is low. A latch circuit that is an inverter, and is a circuit that holds both forward and reverse outputs in which two inverters are connected across each other when a positive phase clock is low and a negative phase clock is high.