JPS6352247A - Memory device - Google Patents

Abstract

PURPOSE:To decrease the access frequency and to shorten the data transfer time by using an access data switching means which selects plural parts after changing the selecting positions. CONSTITUTION:Each of memory devices #0M-#3M of the same constitution consists of memories M0-M7, bit interfaces BTI0-BTI7, a pixel interface PXI-0, and a timing command control TCC including a timing control TC and a command control CC. The control CC receives the line selection reading commands from address buses A0-A7 by the control signals CSW, CAS and WE and outputs these signals to the control TC. The control TC actuates the access data switching means in the interfaces BTI0-BTI7 and advances successively the present data access addresses of memories M0-M7 to output successively the data on the memories M0-M7 to output buses IO0-IO7.

Description

DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to a memory device that can store image data and the like, and can also transfer the stored data at high speed.

"Prior Art" The capacity of a frame buffer in which image data for image display is stored is proportional to the size and resolution of the display area, and also depends on the number of display screens (for example, when multiple screens are prepared in advance). Proportional. When displaying in color, the frame buffer has a capacity corresponding to the number of display colors.

For example, ■ When performing 6-color display, 4 bits are required as the color code, so the frame buffer is
As shown in Fig. 19, the frame memory FMO for four sides
Requires 7 FM3s. In this case, each frame memory P
Data surrounded by a broken line at the same bit position of M O to FM3 (the direction of this broken line is hereinafter referred to as the pixel direction)
corresponds to one dot on the display screen. When displaying an image, each frame memory F M O to F M3
For each pixel, data is read out sequentially as the display surface is scanned, thereby making it possible to display multiple colors. In addition, in reality, in response to higher image quality, dual port memories are provided in parallel on four sides as frame memories FMO to FM3, and pixel data is read out synchronously from the norial data output terminal of each chip. The method is generally adopted.

"Problems to be Solved by the Invention" By the way, as mentioned above, in a device where the storage section is composed of a memory with multiple planes, data transfer is performed for each plane in units of words, or data is transferred in units of pixel data. It may be necessary to do so. In this case, in conventional memory devices, the transfer source surface and address must be specified and read one by one, and the transfer destination surface and address must also be specified and written one by one. A problem arose in that many accesses were required and it took a long time to transfer data.

Also, if the transfer source or transfer destination area spans two consecutive words, if the number of accesses increases further, the bit position of the transfer data must be shifted. , problems of increased transfer time and double chloride processing arose.

This invention was made in view of the above-mentioned circumstances, and its purpose is to reduce the number of accesses and reduce the data transfer rate, and to also An object of the present invention is to provide a memory device that can perform data transfer at high speed even when the memory device exists across two or more locations.

In order to solve the above-mentioned problems, the present invention provides a memory section provided on a plurality of sides with a common address bus, and one memory cycle when accessing each memory section. a selection means for enabling a specific part of the storage area that can be accessed by the memory; and an access data switching means for selecting a plurality of parts by changing the selection position of the selection means within one memory cycle. Equipped with

Further, as a further development of the above invention, in addition to the above structure, a plurality of buffers for transmitting and receiving data to and from a selected portion of the memory section are provided.

``Function'' The access data switching means described above makes it possible to change the selection position of a specific part of the storage area that can be accessed in one memory cycle. Data can be read out in multiple colors, and if selection is performed in the bit direction, data can be read out pixel by pixel without re-applying addresses.

In addition, if multiple buffers are provided to send and receive data to and from selected parts of the memory section, bits can be shifted at high speed even when the transfer source and transfer destination areas span two consecutive words. Adjustment is possible,
Such data transfer is also performed at high speed.

"Embodiments" Hereinafter, embodiments of the present invention will be described with reference to the drawings.

Overall Configuration of Embodiment FIG. 1 is a block diagram showing the overall configuration of an embodiment of the present invention. In this figure, M o−M ? are 1 bit x 64K (or 128K) memories, and each is connected in parallel to form an 8 bit x 64K (or 128K) memory block MBO. BTl and -BTl7 are memories M0 to N・17, respectively.
and data bus 10. This is a bit interface that controls data exchange between PX and PX107 on a bit-by-bit basis.
I-0 is a pixel interface that exchanges data of any one bit in the pixel direction (hereinafter referred to as pixel data) with the data bus l0p-o, and also reads chip select data or plane mask data to be described later. It is a circuit. This pixel interface PXI-0 is a bit interface B
T1. - memory xi via either BTI7,
It is designed to exchange pixel data with either of the bit interfaces BT1, -BTI, and timing command control. It is adapted to supply the circuit TCC.

The timing command control circuit Tcc receives address data supplied from the outside via address buses AO to A7, an output enable signal OE, a write enable signal "iVE," a row address strobe signal RAS, and a column address strobe. Signal C
This circuit controls access to the memory block 'vIBO and controls the timing of each part of the circuit based on AS and the like. In addition, the timing command control circuit T
CC is the bit interface B T I o'=
Memory M according to the value of bit mask data (described later) supplied from B T I 7. - It controls the write enable signal of M7. Furthermore, the timing command control circuit TCC decodes the command data supplied from the address buses AO to A7,
Based on this decoding result, each part of the circuit is controlled as appropriate.

The above-described components constitute the memory device #OM. In this embodiment, a total of 4 memory devices #OM and memory devices #IM to #3M having the same configuration as this memory device #OM and memory devices #IM to #3M having the same configuration as the memory device
It consists of two parts.

In this case, the memory block in each memory device #1M to #3M is MHI-1'viB3, the pixel interface is PXI-1-PXI-3, and the data bus connected to each pixel interface is I Op-
1-10p-3.

FIG. 2 shows the connection state of these memory devices #OM to #3M, and as shown in this figure, each memory device: OM
~#3-1 data bus 10. -107 are commonly connected for each bit, and the data buses Iop-o to l0p-3 of each memory device; OM to #3N1 are each individually wired.

Structure of each part of the embodiment The structure of each part of the constructed circuit will be explained in more detail below.

(1) Overview of operation modes for understanding the configuration First, in order to facilitate understanding of the configuration of each part of the circuit, the operation modes in this embodiment will be briefly explained.

(a) Normal mode This mode is for any one of memory devices #OM to #3M.
In this mode, data is accessed in units of 8 bits for the selected memory device. Data in this mode is input/output via data buses IO0-107. That is, this is a mode in which normal 8-bit parallel access is made to any one of the memory devices #OM to #3 to #1.

Further, this mode is used when a predetermined area in memory blocks MBO to MB3 is used as a bucogram memory area.

(b) Mask mode This mask mode is a mode in which any one or more bits of input/output data can be masked, and any one or more of memory devices #OM to #3M can be masked. be. In this case, there are two types of masks: static ones and dynamic ones.Furthermore, among the dynamic ones, there are those in which mask data is supplied every memory cycle, and those in which the mask data is supplied multiple times during a memory cycle. There are some things. The gist of the present invention is to have a mask mode in which mask data is supplied multiple times during one memory cycle and the mask position changes sequentially.

In addition, the mask mode is divided into a word access mode and a pixel access mode separately from the above, and in the case of the word access mode, the data bus [Oo'=I O7
Input/output of data in the word direction is performed via the data bus l0p-0 to I0p-0 in the pixel access mode.
Data is input and output in the pixel direction via op-, 3.

That is, the word access mode is a mode for accessing data in the word direction (see the - dotted chain line) of memory blocks MBO to MB3 shown in FIG. 19, and when bit masking is performed, it is performed as follows. For example, the first
If you want to access the bs, b, bit (or any one bit) shown in Figure 9, use the memory block MB.
0 in the word direction to access wd, (8 bits), and of this 8-bit data, bits other than bs, t)7 are masked to prohibit access, and b5. b,
Access only.

The pixel access mode is, for example, a mode in which memory blocks MBO to NiB5 shown in FIG. 19 are accessed in the pixel direction (see broken lines), and when bit masking is performed, it is performed as follows. For example, when accessing only the pixel 1) b+, Pb2 pit shown in FIG.
Access bits.

Note that in the mask mode, by setting the mask data to all bits and 60, it is also possible not to mask any bits or any memory device.

The above is an outline of the operation mode in this embodiment.

(n) Composition of each part Next, the configuration of each part of the circuit shown in FIG. 1 will be explained.

Note that since the memory devices #OM to #3M all have the same configuration, the following configuration will be described using the memory device #OM as an example.

[Timing command control circuit TCC] This timing command control circuit TCC is
As shown in Figure 1, the timing control circuit TC
and a command/control circuit CC, the configuration of each of which is shown in FIGS. 3 and 4. Third
In the figure, Ta=Te are control signal input terminals, the terminal Ta receives the row address strobe signal RAS, and the terminal Tb receives the chip select signal C8W specifying whether or not to select the memory device #OM. A column address strobe signal CAS is supplied to the terminal Tc, a write enable signal WE is supplied to the terminal Td, and an output enable signal OE is supplied to the terminal Te. DL is the row address strobe signal RAS
is the delay that creates the delayed signal RASD,
ORI is the row address strobe signal RAS and signal R
This is an OR gate that performs a logical OR with ASD to create a signal RASW with a longer pulse width than the row address strobe signal RAS. LFF 1 is chip select signal C
3 A latch type flip-flop (hereinafter referred to as an L type flip-flop) that captures the WO value at the rising edge of the signal RASW, ANI is an AND gate that detects that normal mode is specified and outputs the normal mode enable signal NME, and AN2 is a mask. Detects that the mode has been specified and generates a mask mode enable signal MME.
AN3 is an AND gate that detects that a command write cycle, which will be described later, is specified and outputs a command enable signal LiCE. L
FF2. LFF3. LFF4 is an L-type flip-flop that takes in the values of the enable signals NME, MME, and MCE at the rising edge of the signal RASW, and outputs the signal NMA9M from its output terminal.
Outputs KA and MCC. Also, A N 4 to A N
9 and ANI8. ANI9 is an AND gate that creates the illustrated signals based on the above-mentioned signals and the control signal supplied from the circuit, and ANIO to AN17 are
Each bit interface BT1. -BTI? The bit mask signal BMo-BMW supplied from the AND gate AN8 is ANDed with the signal WEP supplied from the AND gate AN8,
Memory~1 o=M? (See FIG. 5) write enable signal W E P o −W E P ? It is an and gate that creates. Note that the L type flip-flops LFF1 to LFF4 in the above configuration are configured to latch data when an "L" level signal is supplied to the latch terminals having negative logic.

Next, referring to FIG. 4, the command control circuit C
C will be explained. TadO to Tad7 shown in this figure
are address data input terminals, and these address data input terminals TadO to Tad7 are each connected to the input terminal of the command register 1. A command in this embodiment is specified by an 8-bit command code, and this command code is supplied via an address bus. command register l
latches the command code at the rising edge of the row address strobe signal RAS, and outputs the command data M.
Output as C0 to MC7. The command register l sends data MCO, which is the least significant bit of the command data, to the data terminal DT of the decoding circuit 3 and the input terminal of the decoder 2, and sends data M'CI''MC3 to the 0th to 0th bits of the decoding circuit 3, respectively. Data MC4 to MC6 are respectively supplied to the 0th to 2nd bit input terminals of the main command decoder 4 to the second bit input terminal.In this case, the upper 4 bits of the command data become the main command data, and the lower 4 bits become the main command data. The bits become subcommand data. However, the most significant bit MC7 of the command data is a don't care bit, as seen from the figure.

Here, the value of command data M C0 to M C7 (16
The following table shows the relationship between the command name and the command name.

Table 1 Note that Table 1 lists only commands related to the present invention, and the functions of the listed commands will be described later.

The decoding circuit 3 receives signals PAM, CME, and PME.

It has 0th to 7th D-type flip-flops for outputting BCE, LSE, FSB, DBT, and ROE, respectively, and one of the D-type flip-flops is selected depending on the 3-bit address data supplied to the input terminal. is now selected.

That is, the D type flip-flop whose number corresponds to the 3-bit data supplied to the input terminal is selected. Then, the data supplied to the data terminal DT is supplied to the input terminal of whichever D type flip-flop is selected at that time, and when the output signal MDS of the AND gate AN21 rises, the D type flip-flop is selected. It is now included in the program. That is, depending on the value of command data MCl-MC3, signals PA-1. CME, PME, BCE, LSE, F
Either SB, DBT, or ROE is selected, and the value of the selected signal is the value of command data MCO (“I”/“0”).
“). Also, the AND gate A N 2
2 performs the logical product of the signal PAM and LSE, outputs the result of this operation as the signal BLS, and performs the AND date A N
23 performs an AND operation between the inverted signal of the signal PAM and the signal LSE, and outputs the result of this operation as a signal PLS.

Note that the clear terminal CL of the decoding circuit 3 is supplied with a reset signal from the power-on reset circuit 5, and as a result, when the power is turned on, the above-mentioned 0th to 7th
All of the D type flip-flops are cleared.

The main command decoder 4 outputs a "1" signal from the output end of the number corresponding to the 3-bit data supplied to the input end. This main command decoder 1
is designed to output eight types of control signals, but only the signal RGA related to the present invention is shown in this figure. The main command decoder 4 is enabled only when the signals M and C5T are supplied from the AND gate AN20.

The decoder 2 is enabled only when the signal WE W is supplied from the timing control circuit TC and the signal RGA is supplied from the main command decoder 4, and outputs the signal RPW if the data MCO is "0". , if the data MCO is "L", the signal WPW is output.

[Memory Block MBO] FIG. 5 is a block diagram showing the configuration of memory block MBO, and each memory M0 to N in memory block MBO.
17 takes in the row address output on address bus AO~7 at the rising edge of the row address strobe RAS, takes in the column address on the address bus AO~A7 at the rising edge of the column address strobe CAS, and generates the access address. Determine. During a read cycle, data is output when the signal OE W (output enable signal) rises after the access address is determined and the access is completed, and during a write cycle, the signal ~VEPo-WEPT is output when the access address is determined or after that. Data is written only to the memory where the signal is at a high level.

[Pit Interface BTIi] Figure 6 shows the bit interface BT1i (however,
It is a block diagram showing the configuration of TIO1 (i=0 to 7, and the same applies hereinafter).
) are data input/output terminals. Data input/output terminal Tl
The data input from 0i is sent to the 0th . 2nd/3rd bit input terminal, L
It is supplied to the input terminal of the type flip-flop LFF6 and the input terminal of the L-type flip-flop LFF8. Selector IO has signal PAM “l”
The 0th . Second. Third
The bit input terminal is selected and the data supplied to the terminal Tl0i is output, and the signal PAM is "L" and the signal NMA is "L".
0", the first bit input terminal is selected and the signal DIP supplied from the pixel interface PXI-0 (see FIG. 7) is output. The output signal W D of the selector IO is
T i is supplied to the input terminal of the D-type flip-flop DFF7, and the D-type flip-flop DFF7 is
When the signal w EW supplied from the timing control circuit TC rises, the signal ~VDTi is taken in. The output signal 5RCi of this D type flip-flop DFF7 is connected to the buffer BPF3 and the data bus DT.
i is sequentially controlled and supplied to the corresponding memory Mi (see FIG. 1). In this case, buffer BF
F3 is enabled only when the signal ~VEP supplied from the timing control circuit TC is at "1".

The L type flip-flop LFF 6 is a timing
Data is taken in when the signal RASW supplied from the control circuit TC rises.
The output signal F B M i is supplied to the first bit input terminal of the selector 11 .

The L type flip-flop LFF8 receives a signal LMS T supplied from the timing control circuit TC.
Data is taken in when the second . Third
Supplied to the bit input terminal.

Selector +1 has a positive voltage applied to its 0th input terminal via a pull-up resistor, and also receives signals BCE and B supplied from the command control circuit CC.
When both LS are “0”, select the 0th hit input terminal,
When the signal BCE is “1” and the signal BLS is “0”, the first
Select the bit input terminal, and when the signal BLS is “L”, the signal BC
When E is "0" or "l", the second. The third bit input terminal is selected. This selector 11
The output signal of is supplied to the timing control circuit TC as bit mask data B M i.

BrF2 is a buffer whose input end is connected to the data bus DTi, and whose output end is connected to the data input end of the output data buffer 12 and the input end of the oven drain output buffer BFF5. When the signal OEi supplied from the AND gate AN25 is "L", the output data buffer 12
The data supplied to the input terminal is output to the data bus IOi. BrF3 is an oven-drain buffer whose input end is grounded, and the buffers BFF6 and BFF5 are enabled when the signal 0EPi supplied from the AND gate AN26 is "L", and each The output signal D Oi, -OE P
i to pixel interface PXI-0.

AND gates AN27 and AN28 output signals RW based on signals MKA, BMi, RPMP, and PAM, respectively.
The AND gate A N 26 is a gate that generates the signal RPX and the signal RPX, and the AND gate A N 26 generates the signal 0EPi by ANDing the signal RPX and the signal OEW.

Further, the OR gate 0RIO is a gate that takes the logical sum of the signal RwX and the signal NC3, and the AND gate AN25 takes the AND of the output of the OR gate 0RIO and the signal OEW to create the signal OEi. Further, the OR gate 0RIO is a gate that takes the logical sum of the signal RWX and the signal NCS, and the AND gate AN25 takes the logical product of the output of the OR gate 0RIO and the signal OEW to generate the signal OEi.

[Pixel Interface Figure 7 is a block diagram showing the configuration of pixel interface PXI-0. In this figure, 'rrop
-o is a pixel data input/output terminal, and the data input from this pixel data input/output terminal 'rtop-0 becomes data DIP via the buffer BFF I O, and then is transferred to an L-type flip-flop LFFIO1D-type flip-flop DFPI 1. DFF12, the above-mentioned bit interface BTI is supplied to each input terminal of the L type flip-flop LFF I3.
(It is supplied to each selector 10 (see FIG. 6) in BTI 1 to BTI 7.
When the signal RA SW supplied from (Fig. 3) rises, the data supplied to the input terminal is taken in, and the D
The type flip-flop DFF11°DFF12 and the L-type flip-flop LFF13 receive signals WPW and WPW respectively supplied from the command control circuit CC.
The data supplied to the input terminal is taken in when RPW and signal LMST rise.

Each output signal FCS of the L-type flip-flop LFFlO and the D-type flip-flop DFFI 1, 12.

FWP and FRP are respectively supplied to the first bit input terminals of selectors 15 and 16.17.
A positive voltage is applied to each of the 0th bit input terminals of 7 through pull-up resistors. In addition, selectors 15, 16 .
17 2nd. The output signal FDP of the L-type flip-flop LFF13 is supplied to the third bit input terminal.

The selector 15 selects the 0th bit input terminal when the signal BCE supplied from the command control circuit CC is "0" and the signal PLS is "0", and selects the 0th bit input terminal when the signal PLS is "0".
When the signal PLS is "0" and the signal BCE is "1", the first bit input end is selected, and when the signal PLS is "1" and the signal BCE is "0" or "1", the second and third bits are selected. . Also,
The selectors 16 and 17 each receive a signal PME supplied from the command control circuit CC when the signal PLS is "0".
When is “0”, the 0th bit input terminal is selected and the signal PL
When S is "0" and signal PME is "l", the first bit input terminal is selected, and when signal PLS is "l" and signal PME is "0" or "I", the second and second bit input terminals are selected. Select 3-bit input terminal. In this case, the selectors 16 and 17 are actually one selector, or are described as two selectors for convenience of explanation.

18 is a pixel output data buffer, and when a "■" signal is supplied to the enable terminal E, it outputs the signal supplied to the data terminal to the pixel data input/output terminal Tl0p-0. In this case, if a positive voltage is applied to the data terminal via the pull-up resistor, the bit interface BT
I? Data D0° to DO7 are supplied from. Further, the enable terminal E of the pixel output data buffer 18 is connected to a bit interface BTI o to BTI? From signal -0EPo~
-0EP7 is supplied via an inverter INV5, and a positive voltage is applied to the input terminal of the inverter INV5 via a pull-up resistor.

The above is the configuration of each part of the circuit in this embodiment.

Operation of the 9th Embodiment Next, the operation of this embodiment with the above configuration will be explained.

Although this embodiment has various operation modes as described above, the operation according to the present invention will be mainly described below.

(1) Line select read First, at time t shown in FIG. When the row address strobe signal RAS, the column address strobe signal CAS, and the write enable signal WE are all set to "1", the signal M shown in FIG.
CC rises to the "I" signal and the command write cycle operation begins. Then, in the command write cycle, the command code for line select enable J (first long bus, reference), that is, the command code (09) in 10 decimal notation, is supplied from address buses AO to A7. As a result, command register l inputs the above command code at time t, o (row address strobe signal RAS
command data MC
3. A signal (1001) is supplied to the decoding circuit 3 as MC2, MCI, and MCO. Further, when the signal RASD shown in FIG. 3 rises at time t11, which is a predetermined time after the rise of the row address strobe signal RAS, the signal MCD, which is the output signal of the AND gate AN9, rises at the same time, and as a result, The output signal MDS of the AND gate AN21 shown in FIG. 4 becomes "L" and the above command data is taken into the decoding circuit 3.

As a result, the decoding circuit 3 sets the signal LSE to the "L" signal at time tll. Also at this time, the signal PA
If M is an “l” signal, the signal BLS is an “l” signal, and if signal PAM is a “0” signal, the signal PLS is an “l” signal.
In this case, the signal PAM becomes "0" when the command "word access mode" shown in Table 1 is executed, and becomes "l" when the command "pixel access mode" is executed. It is. Execution of these commands is written at the timing shown in FIG. 1O, similar to the above-mentioned command "line select enable". In addition, in the following explanation, the signal PAM is "1".
It is assumed that the signal is set.

Next, at time t shown in FIG.
When the strobe signal RAS is set to "1", the column address strobe signal CAS is set to "0", and the output enable signal OE is set to "0", a read cycle operation is started. In this case, the write enable signal W
If E is a "1" signal, the mask mode is selected, and if it is a "0" signal, the normal mode is selected (see signals NME and MME shown in FIG. 3). Select the mask mode to make the signal 0''.

Also, as shown in FIG. 8, at time 1. Shortly before , the row address of the area to be accessed is supplied to address buses AO to A7. As a result, the row address is determined at time t1, and the column address is similarly determined at time L2 when the column address strobe signal CAS rises. In short, the access address is determined at time t2. The address determined at this time is common to all memory blocks MBO to MB3 in each memory device #OM to #3M. and,
At time L3, select data specifying which bit of the area accessed from the data buses 100 to 107 is to be selected is supplied. In the case shown in FIG. 8, data bus 10. The select data that sets only the data of "1" to "1", that is, the select data that selects the 0th bit is supplied. As a result, data bus 10. The "l" signal is supplied to the input end of the L-type flip-flop LFF8 (see FIG. 6) in the bit interface BTI0 through the data bus 10. A "0" signal is supplied to the input end of the L-type flip-flop LFF8 in the bit interfaces BTI and -BTI7 through the bit interfaces BTI and -BTI7. Then, when the output enable signal OE is raised at time L4, the signal L M ST shown in FIG. 3 rises, and as a result, the L type flip-flop LFF8 shown in FIG. 6 takes in the input signal. As a result, the output signal FBSi of the L-type flip-flop LFF8 at time t4 matches the value of the select data supplied by the above-described processing. That is, bit interface BT1. The signal FBS in the “L” signal, the bit interface BTI
, ~BTI7, the signals FBS and ~FBS7 become "0" signals. And these signals F B S 1 (i=
0 to 7; the same applies hereinafter) are supplied to the second and third bit input terminals of the corresponding selector 11. Here, selector 11
The signal BLS supplied to the select input terminal of
signal (signal PAM and signal LSE are both “l”)
signal), the selector 11 selects the second or third bit input, so that the signal B M i becomes equal to the signal FBSi.

The function of the signal BMi will be explained below.

First, at the time of memory reading, data read from the memory Mi is outputted to the data bus IOi via the output data buffer 12 after passing through the buffer BFF2 shown in FIG.
5. Data bus l0p-0 (or I Op-
1-10p-3). In this case, if the command "bixel access mode" is executed as described above and the signal P A M is "l", the AND gate AN27 shown in FIG. 6 cannot output the "work" signal. Also, since the signal NC5 supplied to the OR gate 0RIO does not become an "L" signal in the normal mode (see FIG. 3), the output signal OEi of the AND gate A N 25 becomes "
1'' signal, and as a result, the output data buffer 12 is never enabled.

On the other hand, the AND gate 28 outputs the signals MKA and BMiSRP.
If both M P and P A M become “L” signals, “
In this case, the signal M K , A is always an “l” signal in the mask mode, and
Signal RPMP is set as follows.

The signal RPMP is set by executing the command "read plane mask" shown in Table 1. FIG. 11 shows the timing of each signal in the execution of this command. First, as shown in Figure 11 (a), the row address
At time t30 when the strobe signal RAS rises, if the column address strobe signal CAS and the write enable signal WE are "1", a command write cycle is set. The operation up to this point is the same as the case of FIG. 10 described above. However, the value written to the command register l (FIG. 4) at time t30 is (10) in hexadecimal as shown in Table 1.

As a result, of the outputs of the command register I, only the MC4 becomes the "l" signal, and the "■" signal is supplied to the 0th bit input terminal of the main command decoder 4. When the signal MC9T supplied to the enable terminal rises, the main command decoder 4 decodes the input signal and makes the signal RGA at the first output terminal an "L" signal.

In this case, the value of signal M CST is determined by the AND of signal M CD and signal C5MP. In the command write mode, the signal MCD is the signal R.
This signal becomes "1" at the rising edge of ASD (Fig. 3) and maintains the "L" level thereafter.
Since the signal PLS is "0", P (see FIG. 7) is
If the signal BCE is "0", the signal is always "1", and if the signal BCE is "1", the signal has a value corresponding to the signal FCS. Therefore, when writing the command "read plane mask", the signal BCE is "l" and the signal FC8 is "1".
1” or under the condition that signal BCE is “O”,
This is done at the rising edge of the signal RAS. In this case, the signal BCE is "l" when the command "bit/chip select mask enable" is executed and when the command "hit/chip select mask disable" is executed according to the timing shown in FIG. “0” to
becomes. Furthermore, as is clear from FIG.
-o to l0p-3.

As described above, at time t30, the command "read plane mask" is written to the command register l. However, at this time t30, the first
In Figure 1 (A), the signal RASD is “0” as shown by the dashed line.
” signal, the signal M CD does not become an “L” signal (see Figure 3), and as a result, the signal M CS shown in Figure 4
T does not become an “l” signal.

Therefore, the main command decoder 4 is not enabled. Next, at time t31, the row address strobe signal RAS, the signal RASD, and the column address strobe signal CAS1 signal WE all become "
As a result, the main command decoder 4 becomes enabled and sets the signal RGA to "l". Also, at time t3□, the signal W E W becomes "l".
” (see Figure 3), and as a result, the decoder 2 becomes enabled. At this time, since the command data MCO supplied to the input terminal of the decoder 2 is a "0" signal, the decoder 2 is enabled. At this timing, the signal RPW is set to "1". Since this signal RPW is supplied to the clock terminal of the D-type flip-flop DFF12 shown in FIG.
A D-type flip-flop DFF12 takes in the data being supplied to its input.

At this timing, the input/output terminal Tl0p
If a signal of "1" or "0" is supplied from -0 to 'rIop-3, this signal will be transmitted to the buffer BFP shown in FIG.
D type flip-flop DFF I through 10
Incorporated into 2. That is, the value of the signal PRP is determined by the value of the signal supplied at time t31. Since the signal FRP is supplied to the first bit input terminal of the selector 17, the signal PME is "1".
Under the condition that PLS is "0", the value of signal RPMP matches the value of signal FRPO.

The signal RPMP is set as described above.

Therefore, if the value of the signal RPMP is set to "l", the output signal of the AND gate A N 28 shown in FIG. 6 becomes the signal B? It is uniquely determined by vi t.

Since the signal BMi is determined by the value of the signal FBSi in the left read operation mode on this line, it is ultimately determined by the select data supplied to the data bus IOi at time t3 shown in FIG. . That is, at time t4, all signals other than bit interface BTI0 become "0".

As a result, after a predetermined time from time 4, the data bus top
Read data RDT output to -o~10p-3
o is the data of the 0th bit of the accessed byte in each memory section MBO to MB3. For example, assuming that the area E1 shown in FIG. 19 is accessed in common for each memory section, when the above-mentioned select data is supplied, the pixel data [)Xo at the 0th bit position is The read data RDT is folded and output.

Next, at time t shown in FIG. 8, select data for selecting only the first bit is supplied. As a result, the output enable signal OE is enabled by the same operation as described above.
After a predetermined period of time has elapsed from time 11+ when RTD rises, the read data RTD, and the pixel data at the second bit position, are output. That is, according to the above example, pixel data l)X+ shown in FIG. 19 is output. and,
Similarly, pixel data px2. px3...
pxn is output. In this case, n is arbitrary, but since one word in this embodiment is 8 bits, the maximum value is 7.

Through the above operations, data is read in units of pixels. Moreover, as shown in Fig. 8, (n+ 1
)! To read out pixel data of i1, address data is given only once, making it possible to read out a desired number of pixel data within one memory cycle.

(Ill) Line Select Write Next, data writing in units of pixels will be explained with reference to FIG.

First, at time Lo, the row address strobe signal RAS, column address strobe signal CAS, write enable signal W E , and output enable signal OE are set in the same manner as in the above line select read, and the command "line select enable" is set in advance. ” to set the signal LSE to “1”. Then, the row address is determined at time t20 when the row address strobe signal RAS rises, and at time L when the column address strobe signal RAS rises.
The column address is determined at +, thereby determining the address to be accessed. Next, at time t2□, data to be written is supplied from the data bus rop-o-IOp-3, and select data specifying which bit of the accessed area is to be selected is supplied to the data bus 10- 10. Supplied from. In the case shown in FIG. 9, only the data on the data bus IOo is set to “1”.
”, that is, select data that selects only the Oth hit. As a result, in the same way as in the above case, the L type flip-flop LFF8 in the bit interface BTIo is supplied via the data bus ■0°. The "L" signal is supplied to the input terminals of the L-type flip-flops LFF8 in the pit interfaces BT1.-BTI7 via the data buses 10, .about.107. 0'' signal is supplied. Then, when the write enable signal WE is raised at time tt, the signal LMST shown in FIG. 3 rises, and as a result, the L type flip-flop LFF8 shown in FIG. Perform import.

As a result, the output signal FBSi of the L-type flip-flop LFF 8 at time t23 matches the value of the select data supplied by the above-described 1 process. That is, the signal F B in the bit interface BTlo
S o is “L” signal, bit ink face BT1
．． The signals FBS, ~FBS, in ~B T I 7 are “0”
．． ” signals.And these signals P B S 1
(i = 0 to 7; the same applies hereinafter) is the corresponding selector 11
The second. The third bit is supplied to the input terminal.

Here, since the signal BLS supplied to the select input terminal of the selector ll is the "l" signal (signal P
and signal LSE are both “L” signals), selector 11
Alternatively, select the third bit input terminal, and as a result, signal B
M i will be equal to the signal FBSi.

The signal B M o - B M 7 is then supplied to one input terminal of each of the AND gates ANlO to AN17 shown in FIG. The AND gates ANIO to AN17 are connected to the write strobe signals W E P of the memories M0 to M7, respectively.
, ~W E P , and as described above, when only the signal B Mo is an "L" signal, only the write strobe signal 'vV E P o can be output. That is, if the output signal WEP of the AND gate AN8 is a "1" signal, the memory M of the 0th bit.

Data is written only to the

In this case, data W D To is written to all memories M0 in each memory device #OM - #k 3 M. That is, in the example shown in FIG. 19, data is written to pixel pXo.

Here, the conditions for the signal WEP to be "1" are as follows.

First, in the normal mode, the signal CS M P is “
and the signal NCS is an “l” signal;
In the mask mode, it is necessary that the signal W P M P becomes a "1" signal and the signal M W P becomes a "1" signal, and furthermore, under this condition, the signal WE~■ becomes a "l" signal.
”It is necessary to become a signal.The signal WP M P is
It is set in the same manner as the signal RPMP described above. However, in this case, the command "Light Plane Mask"
(see Table 1) is executed according to the timing shown in FIG. 10, and the D type flip-flop DFFII shown in FIG.
Write the value that should be set to .

Next, at time 24 shown in FIG. 9, select data for selecting the first bit is transferred to the data bus 10o-1.
Data to be written is supplied from data buses l0p-0 to l0p-3. Then, at time t2s, when the write enable signal WE is raised, each memory device #OM
~#3 is supplied to the first bit of the access area of N1. That is, in the example shown in FIG.
)X+ is written. Similarly, the second bit.

3rd bit... If the nth bit (n is 7 at most) is enabled in sequence, the pixel data pxt
+ pX 3... pxn can be written sequentially. In this case as well, address data needs to be given only once when writing (n+1) pixel data, as described above and in the case of the 1-do mode, and high-speed data writing is achieved.

(1) Line select read/write in the word direction The above-mentioned operations read and write data in units of pixel data, but in this embodiment, input and output data in the word direction in units of words. Can be done. This case will be explained below.

First, to access in the word direction, execute the command "word access mode" shown in Table 1 at the timing shown in FIG. As a result, the decoding circuit 3 shown in FIG. 4 makes its output signal PAM an "O" signal.

Next, when the command "line select enable" is executed, the output signal LSE of the decoding circuit 3 becomes the "l" signal, and as a result, the output signal P of the AND gate AN23 becomes
LS becomes an “L” signal.

When data is read in units of words, it is performed at the timing shown in FIG. 8 described above, and when data is written in units of words, it is performed at the timing shown in FIG. 9. However, the select data for selecting one of the memory devices (planes) is sent to the data bus top.
-o to l0p-3, and read data and write data are sent and received from data bus 10. -107. This will be explained in more detail below.

First, in the case of data read, select data for enabling one of the memory devices is supplied from data buses l0p-0 to l0p-3 at time t4 shown in FIG. For example, when only the memory device #OM is enabled, the select data supplied to the data bus l0p-0 is set to the "l" signal, and the select data supplied to the data bus l0p-0 is set to the "l" signal.
Set the select data supplied to P-1 to ■op-a to “0”
shall be. As a result, the input terminal of the L type flip-flop LFF 13 in the memory device #OM shown in FIG.
"l" signal is supplied to other memory devices #1M to #3M
A "0" signal is supplied to the upper FF13 of the L type flip-flop. Then, at time t4, when the output enable signal OE rises to the "L" signal,
Since the signal L MST becomes an "L" signal, the above select data is taken into the FF 13 on the L type flip-flop at this point. Then, the output signal FDP of the L type flip-flop LFF 13 is the second . Since the signal PLS is supplied to the third bit input terminal and is an "L" signal, the signal R
Each of PMP, WPMP and signal C5MP is connected to signal F.
Matches the value of DP. The signal RPMP is involved in this read mode, and this signal is supplied to the AND gate AN27 shown in FIG. 6 to control the value of the signal OEi (the signal NCS is not output except in the normal mode). .

That is, when the signal RPMP is "l", the signal O
Ei becomes the "L" signal, and the output data buffer 12 becomes enabled. As a result, the data read from the memory M1 is transferred to the data bus IO via the buffer BFF2 and the output data buffer 12 in sequence.
Output to i. On the other hand, when the signals RP to IP are "0" signals, the AND gate A N 27 is "1".
Since no signal is output, output data buffer 1
2 is not enabled and read data is not output.

Therefore, in the above case, one word of data is output only from the memory device #OM.

Then, in the same manner, memory devices #IM to #3N1
By sequentially supplying select data for selecting , data can be read word by word for each overlapping color within one memory cycle without resupplying address data.

Next, when writing data in units of words, the ninth
At time 111 shown in the figure, for example, memory device #O
Select data for selecting M is sent to the data bus ■op-o~
Supplied from IOP~3. As a result, at time t23, the select data is taken into the upper FF13 of the L-type flip-flop shown in FIG. Output signal FDP
has the same value as In this write cycle, signals WPMP and CSMP are involved in permitting/disabling data writing. That is, as shown in FIG. 3, in the normal mode, unless the signal CSMP is "1", the OR gate OR2 will not become "1", so the write enable signal WEP0~VEP7 will be "1". Similarly to Mako, the write enable signals WEPo-WEp will never become an "I" signal unless the signal WPIVIP is "I" in the mask mode. Therefore, data is written only to the memory device #0M in which the signals W P MP and C8MP are at "L".

From then on, if you supply select data to sequentially select memory devices #1M to #3M in the same way, you will be able to supply word-by-word data to each superimposed color within the memory cycle without having to re-supply address data. Can be written.

Application example of 9 embodiments Next, an application example of the above embodiment will be explained.

FIG. 12 is a block diagram showing the configuration of the first application example. In this figure, 40 is 4 bits x 2 words (16
It is a first-in, first-out memory for bits), and is a first-in, first-out memory for
Pixel data is exchanged with the memory devices #OM~13M. This application example is suitable for performing high-speed data transfer in units of pixels from a source area to a destination area. Then, when transferring data, do the following.

In this embodiment, even if the boundaries of both the source area and the destination area coincide with word boundaries, or if one or both of the source area and destination area are two consecutive words, Even if a word exists across two word boundaries, it can be transferred without interruption to the word boundary. In the following, as a general example, a case where both areas exist between two consecutive words will be explained.

Now, as shown in FIG. 13, byte B1. B2゜B3...
...and part-time job Bl 1. B12. There is data TD1.B13 to be transferred. TD2. TD3...
. is each of the above-mentioned bytes Bl, B2. B3 exists across 4 bits each, and the transfer destination area is byte Bl 1. as shown in the figure. B12. , B13, etc., it is shifted to the upper side by 1 bit and becomes 0. That is, both the source area and the destination area exist across two consecutive words.

In such a case, first, byte Bl is accessed, the select data is sequentially shifted from the 4th bit to the 7th bit, the pixel data is sequentially read out, and this data is stored in the first-in first-out memory 40. let As a result, the first-in-first-out memory 40 contains the fourth to seventh bytes of byte B1.
Bit data is stored. Next, byte B2 is accessed, and the select data is sequentially shifted from the 0th bit to the 7th bit, and the same processing as above is performed. As a result, all bits of data TDI and data TD2 are stored in the first-in/first-out memory 40.
The lower 4 bits of are stored.

Next, byte Bl'l is accessed to write the data in first-in first-out memory 40. In this case, the select data is set so that the first bit of the byte is selected, and thereafter, the data for 7 bits in the first-in/first-out memory 40 is sequentially written while shifting the select data to the upper bit side. . As a result, the byte Bll has the following information as shown in the figure.
The data of the 0th to 6th bits of data TDI are written. Next, byte B3 is accessed, all bits are read out as described above, and the read data is stored in first-in first-out memory 40. At this point, the data stored in the first-in first-out memory 40 is the remaining 1 bit (seventh bit) of the data TDI, all the hits of the data TD2, and the lower 4 bits of the data TD3. Then, when byte B12 is accessed and the 0th to 7th hits are sequentially selected and the output data of the first-in first-out memory 40 is written, the hide B12 has the following information:
As shown in the figure, the 7th bit of data TDI and data TD
The 0th to 6th bits of 2 are written. Thereafter, data transfer is performed by accessing the source side and the destination side alternately in the same manner as described in f. If you do the above,
Even if the data at the transfer source or the transfer destination exists in two consecutive words, it can be freely transferred bit by bit. In this case, first-in first-out memory 4
If 0 has the length of two words, data at the transfer source or destination can be transferred without interruption to the word boundary, regardless of how it spans words. .

FIG. 14 is a block diagram showing the configuration of the second application example. In the figure, 51.52 is 8 bits x P bits (P
is the number of sides, and in this example, 4) first-in
First-out memory, cascaded as shown. 53 uses the output data of the first-in first-out memories 51 and 52 as parallel inputs,
This selector extracts consecutive 8-bit data from the 16-bit data input in parallel according to the control signal of the shift specifying section 54. In this case, the selector 53 and the shift designation section 54 constitute a barrel shifter 55.

In this application example, first, the first address of the source area is accessed, and read processing is performed while sequentially selecting each side at this access address.

As a result, the first-in/first-out memory 51 becomes full with word data on each side of the first address.

Next, the next address in the source area is accessed, and each side of this address is sequentially selected and read processing is performed. As a result, first-in first-out memory 52
stores the data of each side of the first address, and the first-in/first-out memory 51 stores the data of (starting address ÷ 1)
) area data is stored. If data is read from the first-in/first-out memories 51 and 52 in this state, the input terminal of the selector 53 will always be supplied with data at consecutive addresses within the same memory device.

Next, access the destination area, select each side in turn, and write.
Even if the source area spans two consecutive words, by appropriately shifting the extraction bit position of the selector 53, seamless transfer in byte units is possible.

The shift specifying unit 54 instructs the selector 53 which bit should be extracted when the source area spans two consecutive words. This shift specification section 54
For example, the above instruction is given under the control of a CPU or the like.

By doing the above, it is possible to freely transfer byte units no matter where the source area is located.

The selector 53 in this application example has the following functions.

That is, as shown in FIG. 15, the selector 53 selects the lower bits (8-m) of the first-in/first-out memory 52 and the upper m bits of the first-in/first-out memory 51. can be extracted as consecutive bits. With such a function, even though the selector 53 only has a capacity of (8x2) bits, it equivalently has a capacity of (8x3) bits from af as shown in Figure 16. However, the function is the same as extracting consecutive 8 bits within this 2.1 bit range. In this case, when the extraction position of the selector 53 is at the position a1 and when it is at the position a2, the first-in/first-out memories 51 and 52 corresponding to the upper and lower output signals of the selector 53 are The correspondence of output data is reversed. That is, by adopting the above configuration, the transfer direction of each output data of the first-in/first-out memories 51 and 52 can be switched.

Having such a function is extremely advantageous in cases where the transfer order needs to be reversed.

Next, a specific example of the barrel shifter 55 will be described with reference to FIGS. 17 and 18.

In FIG. 17, G, G, .
Of the 16-bit data supplied from 52, predetermined 8-bit data is output.

The extraction position of each gate G is shifted by 1 bit, and even when the gates are arranged separately on the lower side and the upper side of the first-in/first-out memories 51 and 52, as shown in the figure, They are arranged shifted by 1 bit as shown in FIG. The opening and closing of each gate is controlled by the output signal of the decoder 60 that decodes the output signal of the shift specifying section 54, and as a result, the same operation as the equivalent circuit shown in FIG. 16 is performed.

Next, the example shown in FIG. 18 is an example in which a selector 65 is used to configure a barrel shifter. The input terminal of this selector 65 has a first-in first-out memory 5.
1.52 output data are supplied, and any one of these data is selected and output from the output terminal Y. Data selection is performed by a signal supplied to the select terminal. In this example, selectors 65 are provided in parallel for 8 bits corresponding to bits 0 to 7, and each selector 65 is
The signal supplied to the input terminal of the circuit is configured to be softened bit by bit as shown in the figure.

The above is an example of the configuration of the barrel shifter 55, but the barrel shifter 55 is not limited to the above configuration, and various circuit configurations are possible. In short, it is sufficient to implement the circuit shown in FIG. 16 isometrically.

In each of the above application examples, the case where l word is 8 bits is taken as an example, but even when one word is 16 bits, the first-in first-out memory 40 is
It is processed in the same way as in the above case by configuring it with a length of 2 pits (2 words) and setting the width of the first-in first-out memory 51.52 to 16 hits (1 word). I can do it.

Note that the memory element used as a memory block receives a column address strobe signal C when inputting and outputting data.
When requesting AS, the column address strobe signal CAS in the line select read may be controlled by elf, which corresponds to the output enable signal OE, as shown by the broken line in FIG. The same applies when performing line select write.

Furthermore, the connection relationships among the bit interface, pixel interface, timing command control circuit, and memory section and the assignment of various functions are not limited to those shown in the above embodiments, and various modifications are possible.

For example, as shown in FIG. 20, memory blocks 70 to 73 having a memory interface Ml and memory block interfaces 75 to 78 are provided, the memory interface MI is provided with a write bit mask function, and the memory block interfaces 75 to 78 are provided. The pond may have various functions.

Furthermore, if the memory capacity is large, a configuration as shown in FIG. 21 may be used. In this figure, each memory block 80.81 has 4 bits x 64K x 4 planes (4 planes), and each memory block 80.81 is provided with a memory interface M1. in this case,
Each memory interface Ml is configured to exchange data in 4-bit units with the memory block interface VlB+.The memory block interface MBI is configured to transfer data in 8-bit units in the word direction to external circuits. , is configured to exchange data in units of 4 bits in the pixel direction.

In the example shown in FIG. 21, the memory interface M
The functions required for I are a word direction/pixel direction switching function, a read/write bit mask function, a write brain mask function, and a read brain mask function.

As a result, the input/output data of the memory interface MI is switched in the word direction, in this case, word direction data for the selected plane or planes, and in the pixel direction, in this case, for each plane. This is pixel data about the surface. During a read/write cycle, bit masking and brain masking can be performed for each surface.

Next, the functions required for the memory block interface are word direction/pixel direction switching function, read bit mask, read brain mask, data buffer (4
2), and a barrel shifter.

Then, when switching to the word direction, the 4-bit data input/output by each memory interface M1 becomes 8 bits in total, and this 8-bit data is input/output as word data according to the read plane mask. On the other hand, when switched in the pixel direction, the pixel data of each heavy color input/output by each memory interface MI are input/output after being ANDed according to the read bit mask with respect to those corresponding to the same surface.

The data buffer requires 8 bits x 4 planes x 2 words, but the barrel shifter only needs one plane. This is a step in which data is transferred for any one selected surface. For example, data is transferred sequentially from the surface on the front side of the drawing toward the surface on the back side.

"Effects of the Invention" As explained above, according to the present invention, there are memory sections provided on a plurality of sides using a common address bus, and a storage area that can be accessed in one memory cycle when accessing each of the memory sections. and access data switching means that selects a plurality of parts by changing the selection position of the selection means within one memory cycle.
Word-by-word and pixel-by-pixel data transfer can be controlled in each layer, which eliminates the need to re-access each side each time data is transferred, reducing the number of accesses and reducing transfer time. It can be made extremely short.

In addition to the above configuration, if a multi-stage buffer is provided for sending and receiving data to and from a selected area of the memory section, the transfer source or transfer destination area will exist in two consecutive words. Even in such cases, the bit position of the transfer data can be adjusted without increasing the number of accesses, so there is an advantage that bit-by-bit data transfer can be performed at high speed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the overall configuration of an embodiment of the present invention, FIG. 2 is a block diagram showing the connection state of memory devices,
Figure 3 is a block diagram showing the configuration of the timing control circuit TC, and Figure 4 is the command control circuit C.
5 is a block diagram showing the configuration of the memory block, FIG. 6 is a block diagram showing the configuration of the bit interface, FIG. 7 is a block diagram showing the configuration of the pixel interface, FIG. 8 is a timing chart for explaining the operation in the line select read cycle of the same embodiment, FIG. 9 is a timing chart for explaining the operation in the line select write cycle of the same embodiment, FIGS. 1O and 11. are timing charts for explaining the operation of the command write cycle, FIG. 12 is a block diagram showing the configuration of the first application example of the same embodiment, and FIG. 13 is a timing chart for explaining the data transfer state in the application example. 14 is a block diagram showing the configuration of a second application example of the same embodiment, and FIG. 15 is a block diagram showing the configuration of the second application example of the same embodiment.
FIG. 16 is an equivalent block diagram of the selector 53, FIGS. 17 and 18 are block diagrams showing a specific example of the configuration of the barrel shifter 55,
FIG. 19 is a conceptual diagram showing the relationship between a frame buffer and a display surface, and FIGS. 20 and 21 are block diagrams showing other examples of connections between memory blocks and various interface functions in the present invention. MBO~MB3...Memory block, LFF8
゜LFF 13...L type flip-flop (selection means), TCC...timing command control circuit (access data switching means), 40.5
1.52...First-in, first-out memory (multi-stage buffer).

Claims (5)

[Claims] (1) A plurality of memory sections that share a common address bus, and a selection means that enables a specific portion of the storage area that can be accessed in one memory cycle when accessing each of the memory sections. and access data switching means for selecting a plurality of portions by changing the selection position of the selection means within one memory cycle. (2) a plurality of memory sections having a common address bus; and a selection means for enabling a specific portion of the storage area that can be accessed in one memory cycle when accessing each of the memory sections; , access data switching means for selecting a plurality of parts by changing the selection position of the selection means within one memory cycle; and a plurality of buffers for sending and receiving data to and from each part selected by the access switching means. A memory device comprising: (3) a plurality of memory sections having a common address bus; and a selection means for enabling a specific portion of the storage area that can be accessed in one memory cycle when accessing each of the memory sections; , access data switching means for selecting a plurality of parts by changing the selection position of the selection means within one memory cycle; and a plurality of buffers for sending and receiving data to and from each part selected by the access switching means. What is claimed is: 1. A memory device characterized in that the memory units are two-dimensionally arranged in a word direction and a pixel direction, and access is performed by selecting either the word direction or the pixel direction. (4) A common address bus is provided, and
a plurality of memory sections arranged two-dimensionally in the word direction and the pixel direction; a bit position selection means for enabling one of the select positions during common access to each of the memory sections; and one memory cycle. pixel data access control means for changing the selection position of the bit position selection means to select a plurality of bit positions, thereby performing pixel-by-pixel access; and a portion of the selection position selected by the pixel data selection means. A memory device comprising: a plurality of buffers for transmitting and receiving pixel data to and from a plurality of buffers. (5) A common address bus is provided, and
an integer number of memory sections two-dimensionally arranged in word and pixel directions; access surface selection means for enabling only one of the memory sections during common access to each of the memory sections; and one memory cycle. word data access control means for selecting a plurality of planes by changing the selection position of the access plane selection means and thereby accessing in units of words; and word data access control means for storing word data selected by the word data access control means. A memory device comprising: a buffer that outputs two consecutive words of data; and a barrel shifter that extracts one word of bit data from the data and supplies it to the word access means.