JPS6353940A - 半導体装置の自動ワイヤボンデイング方法 - Google Patents

半導体装置の自動ワイヤボンデイング方法

Info

Publication number
JPS6353940A
JPS6353940A JP61197593A JP19759386A JPS6353940A JP S6353940 A JPS6353940 A JP S6353940A JP 61197593 A JP61197593 A JP 61197593A JP 19759386 A JP19759386 A JP 19759386A JP S6353940 A JPS6353940 A JP S6353940A
Authority
JP
Japan
Prior art keywords
bonding
coordinate data
position coordinate
lead frame
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP61197593A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0477461B2 (2
Inventor
Kiyoaki Tsumura
清昭 津村
Hitoshi Fujimoto
藤本　仁士
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP61197593A priority Critical patent/JPS6353940A/ja
Publication of JPS6353940A publication Critical patent/JPS6353940A/ja
Publication of JPH0477461B2 publication Critical patent/JPH0477461B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Wire Bonding (AREA)
JP61197593A 1986-08-22 1986-08-22 半導体装置の自動ワイヤボンデイング方法 Granted JPS6353940A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61197593A JPS6353940A (ja) 1986-08-22 1986-08-22 半導体装置の自動ワイヤボンデイング方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61197593A JPS6353940A (ja) 1986-08-22 1986-08-22 半導体装置の自動ワイヤボンデイング方法

Publications (2)

Publication Number Publication Date
JPS6353940A true JPS6353940A (ja) 1988-03-08
JPH0477461B2 JPH0477461B2 (2) 1992-12-08

Family

ID=16377065

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61197593A Granted JPS6353940A (ja) 1986-08-22 1986-08-22 半導体装置の自動ワイヤボンデイング方法

Country Status (1)

Country Link
JP (1) JPS6353940A (2)

Also Published As

Publication number Publication date
JPH0477461B2 (2) 1992-12-08

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