JPS635543A - Semiconductor chip carrier and manufacture thereof - Google Patents
Semiconductor chip carrier and manufacture thereofInfo
- Publication number
- JPS635543A JPS635543A JP61150348A JP15034886A JPS635543A JP S635543 A JPS635543 A JP S635543A JP 61150348 A JP61150348 A JP 61150348A JP 15034886 A JP15034886 A JP 15034886A JP S635543 A JPS635543 A JP S635543A
- Authority
- JP
- Japan
- Prior art keywords
- adhesive
- semiconductor
- adhesive film
- semiconductor chip
- element layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 56
- 238000004519 manufacturing process Methods 0.000 title description 8
- 239000002313 adhesive film Substances 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 239000000853 adhesive Substances 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 13
- 230000001070 adhesive effect Effects 0.000 claims description 17
- 238000005498 polishing Methods 0.000 claims description 7
- 239000004642 Polyimide Substances 0.000 abstract description 5
- 229920001721 polyimide Polymers 0.000 abstract description 5
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 239000002390 adhesive tape Substances 0.000 abstract 1
- 238000010276 construction Methods 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 239000013078 crystal Substances 0.000 description 5
- 239000012212 insulator Substances 0.000 description 5
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 5
- 238000007796 conventional method Methods 0.000 description 4
- CPLXHLVBOLITMK-UHFFFAOYSA-N Magnesium oxide Chemical compound [Mg]=O CPLXHLVBOLITMK-UHFFFAOYSA-N 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000001534 heteroepitaxy Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000007517 polishing process Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 238000001953 recrystallisation Methods 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 239000006061 abrasive grain Substances 0.000 description 1
- 150000001412 amines Chemical class 0.000 description 1
- 239000008119 colloidal silica Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000395 magnesium oxide Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 235000021395 porridge Nutrition 0.000 description 1
- 239000011029 spinel Substances 0.000 description 1
- 229910052596 spinel Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229920001169 thermoplastic Polymers 0.000 description 1
- 239000004416 thermosoftening plastic Substances 0.000 description 1
Landscapes
- Mechanical Treatment Of Semiconductor (AREA)
- Dicing (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は電子デバイスおよび光エレクトロニクスデバイ
ス等半導体デバイスを用いる産業分野に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to an industrial field using semiconductor devices such as electronic devices and optoelectronic devices.
大規模集積回路（ＬＳＩ）は電子卓上計算機、大型コン
ピュータ号広い分野に用いられており、ＬＳＩ機能とし
ても年々集積度、動作速度の向上、消費電力の低減等が
はかられている。例えばＳｉを用いたＬＳＩをＳｔ基板
上ではなく、絶縁体上に形成して基板の浮遊容量を減ら
して高速性を向上させ、同時にラッチアップやソフトエ
ラーの低減をはかることが試みられている。あるいは又
、集積回路（ＩＣ）や他の機能を有するデバイスを積層
化して高集積化や多機能化をはかることも試みられてい
る。Large-scale integrated circuits (LSIs) are used in a wide range of fields such as electronic desktop calculators and large computers, and the LSI functions are being improved year by year in terms of integration, operation speed, and reduction in power consumption. For example, attempts have been made to form LSIs using Si on insulators rather than on St substrates to reduce the stray capacitance of the substrate and improve high speed, while at the same time reducing latch-up and soft errors. Alternatively, attempts have been made to stack integrated circuits (ICs) and devices with other functions to achieve higher integration and multifunctionality.
このような半導体装置は、通常特別な手法で絶縁体上に
単結晶シリコン膜を成長させたのち、その単結晶シリコ
ン膜にデバイスを形成することによって裏遺される〔例
えば、アイ・イー・イー・イー・エレクトロン・デバイ
ス・レターズ（ＩＥＥＥ Ｅｌｏｅｔｒｏｎ Ｄｅｖｉ
ｃｅ Ｌｅｔｔｅｒｓ）ＥＤＬ−１巻、９９頁、１９８
０）。Such semiconductor devices are usually produced by growing a single-crystal silicon film on an insulator using a special method, and then forming devices on the single-crystal silicon film.・IEEE Eloetron Device Letters
ce Letters) EDL Volume 1, Page 99, 198
0).
単結晶シリコン膜を成長させる特別な手法としては、あ
らかじめ多結晶シリコン膜を二酸化シリコン（Ｓｉ’、
）のような非晶質絶縁体上に堆積しておき、この多結
晶シリコン膜を例えばレーザビームで溶融固化して単結
晶シリコン膜に変換する再結晶化法〔例えばアプライド
・フィジックス・レターズ（Ａｐｐｌｉｅｄ Ｐｈｙｓ
ｉｃｓ Ｌａｔｔｅｒｓ） ４３巻。A special method for growing a single-crystal silicon film is to grow a polycrystalline silicon film in advance by growing silicon dioxide (Si',
), and this polycrystalline silicon film is melted and solidified using a laser beam to convert it into a single crystal silicon film [e.g., Applied Physics Letters (Applied Phys.
icsLatters) Volume 43.
１０２３頁、１９８３）や、シリコンウェーハ上にマグ
ネシアスピネル（ＭｇＡ！ｔＯ４）などの絶縁体単結晶
膜をエピタキシャル成長させたのち、この絶縁体単結晶
膜上にシリコン膜をエピタキシャル成長させる、いわゆ
る、ヘテロエピタキシー法〔例えばジャーナル・オプ・
クリスタル・グロース（Ｊｏｕｒｎａｌ ｏｆ Ｃｒｙ
ｓｔａｌ Ｇｒｏｖｒｔｈ） ７１巻、２５９頁、１９
８５）が用いられる。1023, 1983), and the so-called heteroepitaxy method, in which an insulating single crystal film such as magnesia spinel (MgA!tO4) is epitaxially grown on a silicon wafer, and then a silicon film is epitaxially grown on this insulating single crystal film. [For example, Journal Op.
Crystal Growth (Journal of Cry)
stal Grovrth) Volume 71, Page 259, 19
85) is used.
これら従来の手法では、高品質で、かつ均一性の良い単
結晶シリコン膜が得にくいという大きな欠点が存在する
。例えば前述したヘテロエピタキシ法では格子定数ある
いは熱膨張係数の不整合により結晶欠陥が多く導入され
る。又、レーザのようなビームを用いた再結晶化法では
、゛熱歪に基づく欠陥が導入されたり、再結晶化に要す
る時間が長い等の欠点が存在する。このため、非晶質絶
縁体上にＩＣ＋ＬｓＩを形成することが極めて有効であ
ることがｇ識されてはいるものの設計通りの機能を有す
るデバイスあるいはシステムを製造することもまた極め
て難しいのが現状である。These conventional methods have a major drawback in that it is difficult to obtain a single crystal silicon film of high quality and good uniformity. For example, in the above-mentioned heteroepitaxy method, many crystal defects are introduced due to mismatch in lattice constant or thermal expansion coefficient. Further, recrystallization methods using a beam such as a laser have drawbacks such as introduction of defects due to thermal strain and long time required for recrystallization. For this reason, although it is known that forming IC+LsI on an amorphous insulator is extremely effective, it is currently extremely difficult to manufacture devices or systems that function as designed. be.
本発明の目的は、従来の技術では困難であった非晶質絶
縁体上へのＩＣ，ＬＳＩ の形成を容易にし、更には、
所望の如何なる基板上の如何なる位置にも、所望の半導
体デバイスを部分的に形成することのできる半導体チッ
プキャリヤおよびその製造方法を提供するととくある。The purpose of the present invention is to facilitate the formation of ICs and LSIs on amorphous insulators, which was difficult with conventional techniques, and to
It is an object of the present invention to provide a semiconductor chip carrier and a method for manufacturing the same, in which a desired semiconductor device can be partially formed at any desired location on any desired substrate.
第１の発明の半導体チップキャリヤは接着性フィルムと
この接着性フィルム上に固定された複数の半導体チップ
とを含んで構成される。The semiconductor chip carrier of the first invention includes an adhesive film and a plurality of semiconductor chips fixed on the adhesive film.
また第２の発明の半導体チップキャリヤの製造方法は、
半導体素子層が形成された半導体基板表面のスクライプ
線領域に半導体素子層より深い溝を形成する工程と、前
記溝の形成された半導体基板表面に第１の接着剤を介し
て接着性フィルムを固着する工程と、前記接着性フィル
ム上に第２の接着剤を介して支持台を固着する工程と、
物理化学的研磨法により前記半導体基板裏面を研磨し前
記半導体素子層を露出させる工程と、前記第２の接着剤
を箒希専溶解して分離された半導体素子層を固着した前
記接着性フィルム上より前記支持台を除去する工程とを
含んで構成される。Further, the method for manufacturing a semiconductor chip carrier according to the second invention includes:
A step of forming a groove deeper than the semiconductor element layer in the scribe line region of the semiconductor substrate surface on which the semiconductor element layer is formed, and fixing an adhesive film to the semiconductor substrate surface with the groove formed through a first adhesive. a step of fixing a support base onto the adhesive film via a second adhesive;
a step of polishing the back surface of the semiconductor substrate by a physicochemical polishing method to expose the semiconductor element layer; and a step of dissolving the second adhesive to fix the separated semiconductor element layer on the adhesive film. and a step of removing the support base.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は第１の発明の半導体チップキャリヤの一実施例
の断面図である。FIG. 1 is a sectional view of an embodiment of a semiconductor chip carrier of the first invention.
第１図において、半導体チップキャリヤはポリイミド系
の接着性フィルム１とこの上に接着剤２により固定され
た複数の半導体チップ３とから構成されている。接着剤
２としては例えば、ポリイミド系接着剤で接着性フィル
ム１よりも接着作業温度が低いものを用いる。In FIG. 1, a semiconductor chip carrier is composed of a polyimide adhesive film 1 and a plurality of semiconductor chips 3 fixed thereon by an adhesive 2. In FIG. As the adhesive 2, for example, a polyimide adhesive whose bonding temperature is lower than that of the adhesive film 1 is used.
このように構成された本実施例においては、接着性フィ
ルム１は、はさみやナイフで容易に截断できるため、必
要な半導体チップを切り取り、他の基板の所望の位置に
固着し半導体デバ・イスを部分的に形成することができ
る。In this embodiment configured in this way, the adhesive film 1 can be easily cut with scissors or a knife, so the necessary semiconductor chips can be cut out and fixed to desired positions on other substrates to form a semiconductor device. Can be partially formed.
次Ｋｇ造方法について説明する。Next, the Kg manufacturing method will be explained.
第２図（＆）〜（ｄ）は第２の発明である半導体チップ
キャリヤの製造方法を説明する為の工程順に示したチッ
プの断面図である。FIGS. 2(&) to (d) are cross-sectional views of a chip shown in the order of steps for explaining the method of manufacturing a semiconductor chip carrier according to the second invention.
まず第２図（ａ）に示すように、シリコン基板４の表面
に通常の方法で６４にビットダイナミックＲＡＭに用い
られる複数の半導体素子層８を形成し、スクライプ線分
離領域に半導体素子層３の厚さよシも深い溝５を形成す
る。First, as shown in FIG. 2(a), a plurality of semiconductor element layers 8 used for a bit dynamic RAM are formed at 64 on the surface of a silicon substrate 4 by a conventional method, and the semiconductor element layers 3 are formed in the scribe line isolation region. A deep groove 5 is formed in both thickness and thickness.
次に第２図（ｂ）に示すように、ポリイミド系の第１の
接着剤２人を半導体素子層３上に被覆する。Next, as shown in FIG. 2(b), the semiconductor element layer 3 is coated with two polyimide-based first adhesives.
次に第２図（Ｃ） Ｋ示すように厚さ５０μｍ程度のポ
リイミド系からなる接着性フィルム１を第１の接着剤を
用いて接着させたのち、この上に軟化温度が第１の接着
剤２人の耐熱温度（〜２００℃）よりも低い熱可塑性の
第２の接着剤６を用いて、金属製の支持台７を接着する
。Next, as shown in FIG. 2 (C) K, an adhesive film 1 made of polyimide with a thickness of about 50 μm is adhered using a first adhesive, and then a first adhesive having a softening temperature of A metal support 7 is bonded using a thermoplastic second adhesive 6 whose heat resistance temperature is lower than the heat resistance temperature of two people (~200° C.).
次に第２図（力に示すように物理化学的研磨法によりシ
リコン基板４の裏面を研磨し半導体素子層８を露出させ
る。この工程で各半導体素子層８はシリコン基板４より
分離される。この研磨工程では、例えば砥粒としてコロ
イダルシリカ、化学液として有機アミンを用いると半導
体素子分離領域を形成する二酸化シリコン（Ｓ ＩＯ，
）の研磨加工速度をシリコンの加工速度に比べて１１５
０程度に小さくできる。従って、半導体素子層３よシ深
く形成されたＳｌＯ，層とシリコン基板との境界で、研
磨を自動的に停止させることができる。Next, as shown in FIG. 2, the back surface of the silicon substrate 4 is polished by a physicochemical polishing method to expose the semiconductor element layer 8. In this step, each semiconductor element layer 8 is separated from the silicon substrate 4. In this polishing process, for example, if colloidal silica is used as the abrasive grain and organic amine is used as the chemical liquid, silicon dioxide (SIO,
) compared to the polishing speed of silicon.
It can be made as small as 0. Therefore, polishing can be automatically stopped at the boundary between the silicon substrate and the SlO layer formed deeper than the semiconductor element layer 3.
次にこのような研磨工程を経たのち、加熱して接着性フ
ィルム１を支持台７からはずし、有機容剤で第２の接着
剤６を除去することにより第１図に示した第１の発明の
半導体チップキャリヤが得られる。Next, after undergoing such a polishing process, the adhesive film 1 is removed from the support base 7 by heating, and the second adhesive 6 is removed with an organic solvent, thereby producing the first invention shown in FIG. A semiconductor chip carrier is obtained.
以下従来技術により半導体素子層８表面に配線等を形成
し６４にビット・ダイナミックＲＡＭＫ用いられる半導
体チップ３を完成させる。Thereafter, wiring and the like are formed on the surface of the semiconductor element layer 8 using conventional techniques to complete the semiconductor chip 3 to be used as a bit dynamic RAMK at 64.
このようにして形成された半導体チップ３を切りとり接
着性フィルム１により４インチサイズの石英ガラス基板
表面に接着することにより石英ガラス基板表面の一部に
６４にビット・ダイナミックＲＡＭを形成した。このよ
うにして得られた石英ガラス基板上の６４にビット・ダ
イナミックＲＡＭは正常の動作特性を示した。The semiconductor chip 3 thus formed was cut out and adhered to the surface of a 4-inch quartz glass substrate using the adhesive film 1, thereby forming a bit dynamic RAM 64 on a part of the surface of the quartz glass substrate. The 64-bit dynamic RAM thus obtained on the quartz glass substrate exhibited normal operating characteristics.
本発明の半導体チップキャリヤはデバイスの積層化にも
有効であり、第３図はその一例を示す縦断面図である。The semiconductor chip carrier of the present invention is also effective for device stacking, and FIG. 3 is a longitudinal sectional view showing an example thereof.
すなわち、サファイア基板１０上にＳｔ、、層１１によ
り分離さｎて形成されたＭＯ８ＦＥＴ素子層１２の上に
、６４にビットダイナミックＲＡＭが形成され半導体チ
ップ３を接着性フィルム１により固着することによシ墳
層デバイスを容易に形成できる。That is, a bit dynamic RAM 64 is formed on a MO8FET element layer 12 formed on a sapphire substrate 10 and separated by a layer 11, and a semiconductor chip 3 is fixed by an adhesive film 1. A cylindrical layer device can be easily formed.
上記実施例では半導体素子層としてＳｌからなるＬＳＩ
を用いた場合について示したが、半導体素子層はシリコ
ンに限らず、例えばＧａＡｓの如き■−■化合物半導体
結晶層に形成されたＬＳＩであってもよいことは勿論で
ちる。In the above embodiment, the semiconductor element layer is an LSI made of Sl.
Although the semiconductor element layer is not limited to silicon, it is of course possible to use an LSI formed in a 1-2 compound semiconductor crystal layer such as GaAs, for example.
以上説明したように本発明は、接着性フィルム上に半導
体チップを固着することにより、非晶質絶縁体上へのＩ
Ｃ，ＬＳＩ の形成が容易にできるという効果のある半
導体チップキャリヤおよびその製造方法が得られる。As explained above, the present invention is capable of attaching I/O onto an amorphous insulator by fixing a semiconductor chip onto an adhesive film.
A semiconductor chip carrier and a method for manufacturing the same are obtained which are effective in facilitating the formation of a C,LSI.
第１図は第１の発明の半導体チップキャリヤの一実施例
の断面図、第２図（ａ）〜（ｄ）は第２の発明の半導体
チップキャリヤの製造方法の一実施例を説明するための
工程順に示したチップの断面図、第３図は本発明の半導
体チップキャリヤを用いてデバイスを積層化した一例の
断面図である。
１・−・・・接着性フィルム、２・・・−・接着剤、２
Ａ−・・・第１の接着剤、３・・・・・・半導体チップ
、４・・・・・・シリコン基板、５・・・・・・溝、６
・・・・−・第２の接着剤、７・・−・・・支持体、８
・・・・・・半導体素子層、１０・・・・・・サファイ
ア基板、１１・・・・・・５１０１層、１２・−・・・
・ＭＯ８ＦＥＴ素子層。
Ｍｌス
粥３図
第Ｚ図FIG. 1 is a sectional view of an embodiment of the semiconductor chip carrier of the first invention, and FIGS. 2(a) to 2(d) are for explaining an embodiment of the method for manufacturing the semiconductor chip carrier of the second invention. FIG. 3 is a cross-sectional view of an example of a device stacked using the semiconductor chip carrier of the present invention. 1... Adhesive film, 2... Adhesive, 2
A-...First adhesive, 3...Semiconductor chip, 4...Silicon substrate, 5...Groove, 6
......Second adhesive, 7...Support, 8
... Semiconductor element layer, 10 ... Sapphire substrate, 11 ... 5101 layer, 12 ...
・MO8FET element layer. Ml Su Porridge 3 Figure Z
Claims (2)
た複数の半導体チップとを含むことを特徴とする半導体
チップキャリヤ。(1) A semiconductor chip carrier comprising an adhesive film and a plurality of semiconductor chips fixed on the adhesive film.
ライプ線領域に半導体素子層より深い溝を形成する工程
と、前記溝の形成された半導体基板表面に第１の接着剤
を介して接着性フィルムを固着する工程と、前記接着性
フィルム上に第２の接着剤を介して支持台を固着する工
程と、物理化学的研磨法により前記半導体基板裏面を研
磨し前記半導体素子層を露出させる工程と、前記第２の
接着剤を溶解して分離された前記半導体素子層を固着し
た前記接着性フィルム上より前記支持台を除去する工程
とを含むことを特徴とする半導体チップキャリヤの製造
方法。(2) forming a groove deeper than the semiconductor element layer in a scribe line region on the surface of the semiconductor substrate on which the semiconductor element layer is formed; and adhesion to the surface of the semiconductor substrate on which the groove is formed via a first adhesive; a step of fixing a film; a step of fixing a support on the adhesive film via a second adhesive; and a step of polishing the back surface of the semiconductor substrate by a physicochemical polishing method to expose the semiconductor element layer. and removing the support base from above the adhesive film to which the separated semiconductor element layer is fixed by dissolving the second adhesive.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61150348A JPS635543A (en) | 1986-06-25 | 1986-06-25 | Semiconductor chip carrier and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61150348A JPS635543A (en) | 1986-06-25 | 1986-06-25 | Semiconductor chip carrier and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS635543A true JPS635543A (en) | 1988-01-11 |
Family
ID=15495027
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61150348A Pending JPS635543A (en) | 1986-06-25 | 1986-06-25 | Semiconductor chip carrier and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS635543A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02191358A (en) * | 1989-01-19 | 1990-07-27 | Toshiba Corp | Processing of semiconductor device |
| US6479890B1 (en) | 1998-01-22 | 2002-11-12 | Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V. | Semiconductor microsystem embedded in flexible foil |
-
1986
- 1986-06-25 JP JP61150348A patent/JPS635543A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02191358A (en) * | 1989-01-19 | 1990-07-27 | Toshiba Corp | Processing of semiconductor device |
| US6479890B1 (en) | 1998-01-22 | 2002-11-12 | Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V. | Semiconductor microsystem embedded in flexible foil |
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