JPS635543U - - Google Patents
Info
- Publication number
- JPS635543U JPS635543U JP9728686U JP9728686U JPS635543U JP S635543 U JPS635543 U JP S635543U JP 9728686 U JP9728686 U JP 9728686U JP 9728686 U JP9728686 U JP 9728686U JP S635543 U JPS635543 U JP S635543U
- Authority
- JP
- Japan
- Prior art keywords
- output
- buffer
- state
- microprocessor
- tri
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000872 buffer Substances 0.000 claims description 7
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Bus Control (AREA)
Description
第１図は本考案に係るマイクロプロセツサの出
力回路の一例を示す要部構成図、第２図は動作説
明のためのタイムチヤート、第３図はインサーキ
ツトエミユレータについて説明するための図、第
４図は従来のマイクロプロセツサの出力回路の一
例を示す構成図である。
１……ターゲツトボード、２……マイクロプロ
セツサ、３……ＩＣソケツト、４……プローブ、
Ｇ１１，Ｇ２１，Ｇ３〜Ｇｎ……トライステート
・バツフア、Ｇｉ……バツフア、Ｇｃ……ゲート
。
Fig. 1 is a main part configuration diagram showing an example of the output circuit of a microprocessor according to the present invention, Fig. 2 is a time chart for explaining the operation, and Fig. 3 is a diagram for explaining the in-circuit emulator. , FIG. 4 is a block diagram showing an example of an output circuit of a conventional microprocessor. 1...Target board, 2...Microprocessor, 3...IC socket, 4...Probe,
G 11 , G 21 , G 3 to G n ... tristate buffer, G i ... buffer, G c ... gate.
Claims (1)
あつて、外部からの制御信号を受信するためのバ
ツフアと、このバツフアの出力状態が優先的に与
えられる制御用の信号に基づきその出力端の状態
が制御されるように構成された信号出力用のトラ
イステート・バツフアを具備し、外部からの制御
信号が与えられないときには内部の制御条件に依
存するが、外部からの制御信号が与えられたとき
は内部の条件に拘らず一斉にトライステート・バ
ツフアの出力端がハイ・インピーダンスになるよ
うに構成したことを特徴とするマイクロプロセツ
サの出力回路。 A buffer circuit for the output of a microprocessor, which includes a buffer for receiving control signals from the outside, and a control signal that controls the state of the output terminal based on a control signal that gives priority to the output state of this buffer. It is equipped with a tri-state buffer for signal output configured to be 1. A microprocessor output circuit characterized in that the output terminals of tri-state buffers are configured to have a high impedance regardless of the conditions.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9728686U JPS635543U (en) | 1986-06-25 | 1986-06-25 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9728686U JPS635543U (en) | 1986-06-25 | 1986-06-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS635543U true JPS635543U (en) | 1988-01-14 |
Family
ID=30964082
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9728686U Pending JPS635543U (en) | 1986-06-25 | 1986-06-25 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS635543U (en) |
-
1986
- 1986-06-25 JP JP9728686U patent/JPS635543U/ja active Pending
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