JPS6410677U - - Google Patents
Info
- Publication number
- JPS6410677U JPS6410677U JP10475387U JP10475387U JPS6410677U JP S6410677 U JPS6410677 U JP S6410677U JP 10475387 U JP10475387 U JP 10475387U JP 10475387 U JP10475387 U JP 10475387U JP S6410677 U JPS6410677 U JP S6410677U
- Authority
- JP
- Japan
- Prior art keywords
- gate
- tri
- integrated circuit
- fault detection
- circuit device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Tests Of Electronic Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Description
第１図はこの考案の一実施例である集積回路装
置を示す論理回路図、第２図は従来の集積回路装
置を示す論理回路図である。
図において、１……トライステートゲート(1)
、２……トライステートゲート(2)、３……トラ
イステートゲート(3)、４……データ信号(1)、５
……データ信号(2)、６……データ信号(3)、７…
…コントロール信号(1)、８……コントロール信
号(2)、９……コントロール信号(3)、１０……デ
ータ信号(4)、１１……ゲート(4)、１２……ゲー
ト(5)、１３……ゲート(6)、１４……ゲート(7)
、１５……ゲート(8)、１６……ゲート(9)、１７
……ゲート(10)、１８……出力信号、１９……単
一縮退故障検出回路である。なお、図中、同一符
号は同一、又は相当部分を示す。
FIG. 1 is a logic circuit diagram showing an integrated circuit device which is an embodiment of this invention, and FIG. 2 is a logic circuit diagram showing a conventional integrated circuit device. In the figure, 1...tristate gate (1)
, 2... tri-state gate (2), 3... tri-state gate (3), 4... data signal (1), 5
...Data signal (2), 6...Data signal (3), 7...
...Control signal (1), 8...Control signal (2), 9...Control signal (3), 10...Data signal (4), 11...Gate (4), 12...Gate (5), 13...Gate (6), 14...Gate (7)
, 15...Gate (8), 16...Gate (9), 17
...gate (10), 18...output signal, 19...single stuck-at fault detection circuit. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
するトライステートゲートのコントロール信号の
単一縮退故障検出回路を備えたことを特徴とする
集積回路装置。 An integrated circuit device, such as an LSI, comprising a single stuck-at fault detection circuit for control signals of tri-state gates that drive the same signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10475387U JPS6410677U (en) | 1987-07-08 | 1987-07-08 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10475387U JPS6410677U (en) | 1987-07-08 | 1987-07-08 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6410677U true JPS6410677U (en) | 1989-01-20 |
Family
ID=31336749
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10475387U Pending JPS6410677U (en) | 1987-07-08 | 1987-07-08 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6410677U (en) |
-
1987
- 1987-07-08 JP JP10475387U patent/JPS6410677U/ja active Pending
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