JPS6358375B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device and a method for manufacturing the same, and particularly to bipolar transistors in which a first conductivity type substrate, a second conductivity type well, and a first conductivity type diffusion layer are used as a collector, a base, and an emitter, respectively. The present invention relates to a complementary MiS semiconductor device on a substrate and a method for manufacturing the same.

As shown in FIG. 1, regions of a conductivity type different from that of the substrate, called wells 2 and 3, are formed on one semiconductor substrate 1, and regions of conductivity type opposite to each other, that is, a P channel and a P channel, are formed on the surfaces of the substrate and the well. In a complementary MOS semiconductor device in which N-channel MOSFETs (insulated gate field effect transistors) Q ₁ and Q ₂ are formed, a bipolar transistor is constructed simultaneously on the same substrate by a substrate 1, a well 3, and a diffusion layer 4 in the well region. It is proposed to form Q ₃ .

However, in this method, when the diffusion layer 4 forms the source and drain of the MOSFET in the well,
Since it is formed by simultaneous diffusion, the depth of the diffusion layer 4 is the same as the diffusion depth of the source and drain (0.5 to 1.0 μm).
It was found that the base length of the bipolar transistor (L _B in Figure 1) cannot be shortened, and that there is a limit to high-speed operation.

The present invention has been made to eliminate the above-mentioned drawbacks, and its object is to obtain a complementary type (MOS) semiconductor device having bipolar transistors capable of high-speed operation on the same substrate.

FIG. 2 schematically shows a semiconductor device according to the present invention. In the same figure, n ^-substrate 1
Source S ₁ and drain due to P diffusion on part of the surface of
D ₁ and gate G ₁ constitute P-channel MOSFET Q ₁ , and the source is formed by n diffusion on the surface of P ^- well 2.
N-channel with S ₂ , drain D ₂ , and gate G ₂
A bipolar transistor Q ₄ is formed in which the substrate ₁ , the P ^- well 3, and the in-well diffusion layer 4 constitute a collector, a base, and an emitter, respectively. At this time, the emitter diffusion layer can be formed deeply independently of the N-channel source and drain, allowing high-speed operation of the bipolar transistor. With this invention, in order to increase the speed of MOSFETs, the source drain is formed shallowly, and the emitter diffusion layer, which was formed at the same time as the source drain, is also shallow. This overcomes the limitation, and a bipolar transistor capable of high speed operation is formed. can do.

FIG. 3 shows a modification of the present invention. In this example, P
The source and drain of channel MOSFETQ ₁ are formed shallowly, but the N channel on the well side
The source and drain contact areas and the emitter diffusion layer for one part of the MOSFET are simultaneously formed and deepened. Even with this structure, the diffusion depths d ₁ and d ₂ of the source and drain, which determine the characteristics of the MOSFET, can be made shallow, increasing the speed of the MOSFET and independently obtaining deep emitter diffusion. A bipolar transistor element is obtained.

FIGS. 4a to 4h show specific manufacturing steps for the complementary MOS semiconductor device of the present invention. A detailed explanation will be given below corresponding to each process diagram.

(a) An n ^- Si substrate 1 is prepared, boron (B) is ion-implanted using a part of the SiO ₂ film 5 as a mask,
P ^- well regions 2 and 3 are formed.

(b) Using a mask made of silicon nitride (Si ₃ N ₄ ), etc., perform selective oxidation at a temperature of about 900°C to 1100°C to form a field oxide thick film 6.
, and then substrate 1 and wells 2 and 3.
Thin gate oxide films 7 and 8 are formed on the surface of the active region (including the bipolar transistor emitter diffusion layer portion).

(c) Using photoetching technology, the gate oxide film is opened to expose part of the source and drain regions on the well side and the emitter diffusion layer.

(d) By forming a polysilicon layer 9 on the entire surface and performing phosphorus treatment, an emitter diffusion layer 4 and an n ⁺ source/drain contact portion 1 are formed in the window opening.
For example, 0 and 11 are formed at a depth of 1 μm.

(e) Etch a portion of the polysilicon layer and remove the polysilicon layer.
The Si gates 12 and 16 are left.

(f) PSG well 2 side surface and emitter diffusion layer.
(phosphosilicate glass) 13, etc., and using the polysilicon gate 12 on the substrate side as a mask,
The gate oxide film on the source and drain regions is etched away in a self-aligned manner, and boron treatment or ion implantation is performed to form P diffusion sources 14 and 15 to a depth of, for example, 0.5 μm.

(g) After this, the surface of the substrate 1 side is covered with PSG (phosphosilicate glass) 17, and the polysilicon gate 1
By using 6 as a mask, phosphorus (P) or arsenic (As) is diffused or ion-implanted to form an n source 18 and a drain 19 to a depth of, for example, 0.5 μm.

(h) After this, a passivation film 20 is formed using PSG or the like on the entire surface, and is made of aluminum (Al) to be in contact with the source drain on the substrate 1 side, the source drain contact part, emitter, and base contact part on the well 2 side, respectively. Electrode 2
1 to complete a P-channel MOSFET, an n-channel MOSFET, and a bipolar transistor.

As a modification of the above manufacturing method, the same effect can be obtained by leaving the polysilicon on the emitter diffusion layer in step (e) and performing the same steps thereafter to form a bipolar transistor with the structure shown in Figure 5. is obtained.

In this way, by forming the emitter diffusion layer of a bipolar transistor at the same time when polysilicon is treated with n ⁺ phosphorus using a direct contact structure between polysilicon and the diffusion layer, the diffusion layer can be formed deep and the base length of the bipolar transistor can be increased. It can be shortened and can operate at high speed.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view schematically showing a complementary MOS semiconductor device having bipolar transistors on the same substrate, and FIG. 2 is a cross-sectional view schematically showing an embodiment of a complementary MOS semiconductor device having bipolar transistors according to the present invention. 3 are sectional views schematically showing other embodiments of the present invention, and FIGS. Figure 5 shows a complementary type using another manufacturing process according to the present invention.
FIG. 2 is a cross-sectional view of a MOS semiconductor device. 1...Si substrate, 2...P ^- well, 3...P ^- well which becomes the base of the bipolar transistor,
4... Emitter diffusion layer, 5... Surface oxide film, 6...
...field oxide film, 7,8...gate oxide film,
9...Polysilicon, 10,11...n source,
Drain contact part, 12...P channel
MOSFET polysilicon gate, 13...SiO ₂
Film, 14, 15...P channel source, drain, 16...N channel MOSFET polysilicon gate, 17...SiO ₂ film, 18, 19...N
Channel source drain, 20...PSG film,
21...Aluminum.

Claims (1)

[Claims] 1. An MIS element including a second conductivity type source and drain is formed in a part of the first conductivity type semiconductor substrate, and an MIS element including the first conductivity type source and drain is formed in a second conductivity type well region in the other part of the substrate. In a semiconductor element device formed by forming an element, the first conductivity type source,
Each region of the drain has a shallow part and a deep part,
Electrode contacts to these regions are made on the deep portions, and a bipolar transistor element is constructed within a portion of the substrate, and the emitter layer of this bipolar transistor is formed deeper than the shallow source and drain regions of the MIS element. A semiconductor device characterized by: