JPS635902B2 - - Google Patents

Description

[Detailed Description of the Invention] This invention provides a basic configuration using insulated gate field effect transistors (hereinafter referred to as MOS transistors) in advance, and by adding simple patterns, various circuit configurations can be obtained. A so-called master slice type semiconductor integrated circuit (hereinafter referred to as master slice IC)
This is related to the cell.

Conventionally, as the degree of integration of IC semiconductor integrated circuits increases, the number of components in the device decreases, leading to cost reductions. However, as a result of the dramatic increase in the scale of integration that can be realized, in many types of semiconductor integrated circuits for which demand has increased significantly in recent years, such as random logic circuits, as the degree of integration increases, the versatility decreases and the dedicated There is a tendency to use IC. In that case, it is no longer possible to expect cost reductions due to mass production effects.

In the case of such small-volume, high-mix specialized ICs, the first step to reducing costs is how to shorten the time required for design and manufacturing and how to shorten delivery times.

Generally, when manufacturing an IC, multiple masks are required for each process. Therefore, when there are design changes and various types of products are manufactured, a lot of time and man-hours are spent making masks. They account for a considerable factor in increasing the manufacturing cost of ICs. The master slice method is promising as a means to improve these inconveniences. This method involves batch production up to a certain stage of the manufacturing process that is common to ICs for various uses, and one or two masks (contact holes and metal In this method, the user creates a wiring mask (wiring mask) and performs the remaining processes to manufacture various ICs.

Now, some proposals for master slice ICs are already known, but a method for creating a dedicated IC by having the user write a contact hole mask and a metal wiring mask is proposed in the published patent publication No.
53-45985 "Semiconductor integrated circuit device" is known. However, although this method has the advantage of a high degree of freedom in wiring, it has the disadvantage that the user must make two masks. Another disadvantage is that the manufacturing process for specialization becomes long.

On the other hand, as a master slice IC in which a user writes only a metal wiring mask to create a dedicated IC, the American company INTERDESIGN INC.
MONOCHIP MD-A is known. This is a master slice IC for logic circuits using N-channel Si gate field effect transistors (hereinafter referred to as Si gate MOS transistors).
The user creates a mask for forming aluminum wiring to realize the desired logic circuit. IC manufacturers store wafers that have been processed prior to forming wiring patterns by aluminum etching. The desired IC can be obtained by simply etching aluminum using this wafer and a mask made by the user for forming aluminum wiring. But if the user uses this MONOCHIP
When creating an aluminum wiring pattern using MD-A, the wiring in the direction that intersects the power supply line has a large wiring load capacity, which increases delay time and has the disadvantage that the integration density of logic circuits cannot be increased. .

Therefore, in order to improve this, the inventor of the present invention attempted to divide the continuous drive MOS transistors between cells and provide column-direction wiring between them using a general master slice IC. The results were good and sufficient effects were achieved. However, if we limit the discussion to a cell configuration similar to this MONOCHIP MD-A, when dividing the cells by the wiring area in the column direction, when trying to realize a certain part of the circuit, depending on how it is divided, there may be some problems. The drawback was that wiring was difficult.

Hereinafter, this aspect will be explained in some detail using the drawings, and then the configuration of the present invention will be explained.

Figure 1 shows a chip layout diagram of a typical master slice IC. Chip 1 has 28×8=224 cells Cij arranged in a two-dimensional array. Bonding pad _P1 is installed around the chip.
..., P _i , ..., P ₃₈ are attached. There are also pads V _DD and V _SS for supplying power. There is a wiring area 2 between the input/output buffers BA ₁ , BA ₂ , . . . , BA _i , . . . , BA ₃₈ and the cell array. Further, there is a wiring region 3 between rows between the cells. The output buffer BA _i has the ability to drive TTL or LSTTL.

Figure 2 shows the configuration of cell Cij. In the figure, C ₁ , C ₂
is a cell and its configuration is that of MONOCHIP MD-A. And H _{1 - A 1} - H ₂ , H ₃ - A 3 - _{H 4} , H ₅ - A ₅ - H ₆ provided between C 1 and C ₂ and at both ends, and U that only partially appears in both. ₁ , _U2 , _U3 , and _U4 are the additional wirings devised by the inventor as described above. Commercially available MONOCHIP MD-A does not have this additional wiring. Now, in the configuration shown in Figure 2, each cell has a first power line V _DD , a second power line V _SS ,
It consists of a continuous drive MS transistor Tij and a load MOS transistor Di. In Figure 2, the ○ marks represent contacts. N ₁ , N ₂ ,…, N _i ,
..., N ₁₁ indicates the contact between the aluminum wiring (not shown) and the diffusion layer, L ₁ , L ₂ , ..., _Li , ...,
L ₈ and M ₁ , M ₂ , . . . , M _i , . . . M ₈ indicate contacts between the poly-Si wiring and the aluminum wiring (not shown). In FIG. 2, the first power line V _DD and the second power line V _SS are wired in the row direction using a first type wiring material, such as aluminum. The wiring running in the direction intersecting the power supply line is made of a second type of wiring material, such as poly-Si. And further power line V _SS
The diffusion layer is wired under the cross-under. The problem is where the contact of this cross-under diffusion layer is located.

A mask layout diagram of the circuit of FIG. 2 is shown in FIG. The same numbers as in Fig. 2 indicate the same parts. The diagonal line at the top left indicates poly-Si. The diagonal line at the top right indicates the diffusion layer.

Now, if we use the master slice IC shown in Figure 3,
Consider constructing the random logic circuit shown in FIG. The random logic circuit of FIG. 4 is part of a delay flip-flop circuit with reset. 41 is a data input terminal, 42 is a clock input terminal, 44 is a reset input terminal, and 45 is an output terminal of this circuit. Add this circuit to the third
Figure 5 shows an aluminum wiring mask realized using the master slice IC shown in the figure.

Drive MOS transistors T ₁ and T ₃ are for drive
In order to use MOS transistor T ₂ as a transfer gate, gate electrodes M ₁ and M ₃ are connected to the power supply line V _SS
must be connected to. Therefore, the driving MOS transistor of the reset input terminal is made using the driving MOS transistor _T5 of the adjacent cell.
As a result, the area of the diffusion layer of the output terminal increases, the load capacitance increases, and high-speed operation becomes difficult. Also, since transistors are wasted, the packaging density of the circuit on the chip is reduced. The main reason for this can be said to be the inconvenient position of the contact.

As can be seen from the above, an object of the present invention is to appropriately position the contact hole formed in the diffusion layer of the driving MOS transistor of a master slice IC in which transistors are arranged in a two-dimensional array. The object of the present invention is to solve the above drawbacks and realize a high-speed, high-density random logic circuit.

According to the invention, the first
At least three or more drive MOS transistors are connected in series for each cell in a region sandwiched between the second power supply line and arranged in parallel with the power supply line, and one of these drive MOS transistors is From the contact formed on the source/drain connection connecting the first and second wires in series, the column direction wire is further drawn out beyond the second power supply wire, and a contact is also provided at the end thereof. , a gate wiring extending in the column direction to a position beyond the first and second power supply lines and having contacts at both ends is provided for the first driving MOS transistor from the end. A master slice semiconductor integrated circuit cell is obtained in which a large number of cells are arranged in a two-dimensional matrix, characterized in that contacts are also formed at positions sandwiched between the second power supply line and the second power supply line.

Next, an example of implementation of the present invention will be described in detail with reference to the drawings.

FIG. 6 shows the configuration of a cell that is an embodiment of the present invention. This cell has a first power supply line V _DD , a second power supply line V _SS , a continuous driving MOS transistor T ₁₁ ,
T ₁₂ , T ₁₃ , T ₁₄ and load depletion type M
It consists of an OS transistor _D1 . In Fig. 6, the ○ marks represent contacts. N ₁ , N ₂ ,…N _i ,…,
_N16 indicates a contact between a wiring made of a first type wiring material such as aluminum (not shown) and a diffusion layer;
L ₁ , L ₂ , ..., Li, ..., L ₁₄ , and M ₁ , M ₂ , ...,
Mi _. In Figure 6, the first power line V _DD and the second power line V _SS
are wired in the row direction using aluminum, for example.

A mask layout diagram of FIG. 6 is shown in FIG.
The same numbers as in Fig. 6 indicate the same parts. The upper left diagonal line indicates poly-Si, for example. For example, the diagonal line at the top right indicates a diffusion layer.

The flip-flop circuit with reset shown in FIG. 4 will be realized using the cells of the present invention shown in FIGS. 6 and 7. The result is as shown in FIG. As is clear from a comparison between FIG. 5 and FIG. 8, MOS transistors are effectively utilized in FIG. 8 in which the present invention is implemented. For driving
Since the MOS transistor _T11 is used as a transfer gate, the gate _M3 of the driving MOS transistor _T12 is connected to the power supply line _VSS . The NOR circuit can be made using driving MOS transistors _T13 and _T14 , and this circuit can be realized with one cell. The area of the diffusion layer of the output terminal 5 of the NOR circuit is also smaller than that of the conventional example shown in FIG. 5, and as a result of the small load capacitance, high-speed operation is possible.

Also, since the driving MOS transistor _T11 has two gate contacts _L2 and _L7 , the clock signal line Φ and contacts _L2 and _L7 are alternately wired on both sides of the power supply line _VDD . By doing so, a circuit using a clock signal can be easily realized.

By using the present invention, there is no particular difficulty in using it when creating various other functional blocks. When users create various circuits using the master slice method, it is applied to sequential circuits, not combinational circuits. When designing a sequential circuit with LSI,
A delay flip-flop with a reset function is used to initialize the flip-flop. If this flip-flop is not used, the output will not be determined when the power is turned on, making inspection difficult. The rate at which a user uses a delay flip-flop with reset on a certain master slice varies depending on the sequential circuit to which it is applied, but is thought to be about 10% to 40% of the chip area. One delay flip-flop with reset consists of 14 NMOS transistors and uses many unit cells. Conventional contact locations use six cells. However, according to the present invention, it is only necessary to use four cells, and the occupied area can be reduced to 2/3. When N delay flip-flops with resets are used, N×1/3 cells are left over, so other functional blocks can be integrated and the device can be made smaller.

As explained above, the present invention provides a master slice in which transistors are arranged in a two-dimensional array.
By locating IC contacts in appropriate locations, users can create various circuits with high density and high speed using, for example, a single aluminum wiring mask.

[Brief explanation of the drawing]

Figure 1 shows an overview of the chip layout of a general master slice IC, Figure 2 is a circuit diagram of a conventionally known cell, Figure 3 is its mask layout, and Figure 4 is a flip-flop with reset. Figure 5 shows an example of the circuit in Figure 4.
Conventional master slice IC shown in Fig. 3
6 is a cell configuration diagram showing an embodiment of the present invention, FIG. 7 is a mask layout diagram thereof, and FIG. 8 is a diagram of the present invention shown in FIGS. 6 and 7. FIG. 5 is a mask layout diagram when the circuit of FIG. 4 is realized using the cells of FIG. As is clear from the comparison between FIG. 2 and FIG. 6, the driving MOS transistors are connected in series between the first and second power supply lines V _DD and V _SS in parallel with them. T 12, the second from the end, and T ₁₂ , the third from the end.
Contacts in source-drain connection with T ₁₃
Contact B ₃ that was drawn out from N ₃ across the second power supply line is connected to the first T ₁₁ and the second from the end.
Move it between T ₁₂ and become N ₈ , and the second from the end
The feature lies in the fact that the contact _A2 , which was formed in the middle of the gate wiring of _T12 , was moved from the end to the middle of the gate wiring of the first _T11 , forming _L7 . In the figure, other main symbols indicate the following. 1...Master slice IC chip, 2...
...Wiring area, 3...Interrow wiring area, Cij...Cell,
P _i ...Bonding pad, Ti...Drive MOS
Transistor, Di...Load MOS transistor,
Li, M _i , Ei, Bi, Ai...Contact, 41...
Data input terminal, 42...Clock input terminal, 4
4...Reset input terminal, 45...Output terminal.

Claims (1)

[Claims] 1 At least three or more driving MOS transistors are connected in series for each cell in a region sandwiched between first and second power supply lines formed in parallel and arranged in parallel with the power supply lines. , from the contact formed in the source/drain connection connecting the first and second driving MOS transistors in series, the column direction wiring is further extended beyond the second power supply line. A contact is also provided at the end of the pulled out gate wiring, which extends in the column direction to a position beyond the first and second power supply lines, and has contacts at both ends.The gate wiring is connected from the end to the first driving MOS transistor. A master slice formed by arranging a large number of cells in a two-dimensional matrix is characterized in that a contact is also formed at a position sandwiched between the first and second power supply lines in the middle of the gate wiring. Semiconductor integrated circuit cell.