JPS6360648A - Network control system - Google Patents

Abstract

PURPOSE:To prevent the increase in load of a line connection control section and to improve the efficiency of the processing of a network control signal by sending a parallel reception data when it is detected that the network state signal received newly differs from the preceding network state signal. CONSTITUTION:When a level signal (network state signal) is received by a level signal reception circuit PRV, it is stored in a register 23, and the preceding level signal stored in the register 23 is transferred to a register 24. Contents of the registers 23, 24 are compared by exclusive OR gates 251, 252 and if they differ from each other, a gate control circuit 261 is controlled and the contents of the registers 23, 24 are transferred to a shift register 262. When the transfer is finished, serial transfer is started to a serial/parallel conversion circuit 27, which applies serial/parallel conversion by a start-stop synchronous motor and transfers a parallel data to a lien adaptor control section LAC.

Description

[Detailed Description of the Invention] [Summary] In order to simplify the network control interface circuit in a line control device, by adding a start bit and a stop bit to a network status signal and sending it to the serial/parallel conversion circuit, Alternatively, by characterizing the network status signal, it is possible to receive the network status signal using the same circuit as the information signal.

[Industrial application field] The present invention relates to a network control system in a line control device.

When the subscriber telephone network is used for data communication, signals for controlling the subscriber telephone switching network connection (activation and recovery of the central office exchange, sending selection signals, detection of paging signals, etc.) must be processed.

Conventionally, these network status signals have been controlled using a signal line separate from that used for transferring information signals.

Recently, network status signals have been multiplexed with information signals for control, and it is necessary to process network status signals more efficiently.

[Conventional technology] FIG. 6 is a configuration diagram of an apparatus to which the present invention is applied.

In the figure, IFC is an interface control unit that controls the interface with a higher-level device (host computer).

MM is a storage unit that stores communication control programs and data for transmission and reception.

CC is a main control unit that reads and executes a communication control program stored on the storage unit MEM.

Based on instructions from the main control unit CC, the LAC connects the line connection unit (
The data M), the line connection control section (LAC), and the main control section (CC) are connected to each other through a common bus between the LA) and the storage section (MEM).

The LA converts bit serial data from the line into parallel data, converts parallel data from the line connection control unit (LAC) into bit serial data, and performs network control based on instructions from the line connection control unit (LAC). This is the line connection part.

FIG. 7 is a diagram illustrating processing of network status signals according to the prior art.

In the network control device, the line signal is separated into an information signal (2) and a network status signal (2).

The information signal ■ is serial/parallel converted in the serial/parallel conversion circuit (URT) and converted into a character signal (CHR).
It is entered into the line connection control unit (LAC) as a.

The network status signal ■ is received by the network status signal receiving circuit (PRV) and stored in the peripheral control register 1 (PSTRI). Previously received network status signals are stored in peripheral control register 2 (PSTR2).

The comparator (COMP) is connected to peripheral control register 1 (PST
RI) and peripheral control register 2 (PSTR2), and if they are different, the line connection control unit (LAC
') generates an interrupt signal (IRQ).

Line connection control unit (LAC) that receives the interrupt signal (IRQ)
reads the contents of peripheral control register 1 (PSTRI) and processes the network status signal.

[Problems to be Solved by the Invention] As explained above, since the conventional network status signal processing is an interrupt-based process, the line connection control unit (LAC
”) had the problem of increasing the load.

The present invention aims to provide a new network control system that solves these conventional problems.

[Means for solving problems] FIG. 1 shows a block diagram of the principle of the network control system of the present invention.

FIG. 1 Ta) is a block diagram of the principle of the first invention.

In the figure, ■ is an information signal line, and ■ is a network status signal line.

1 is the line connection control unit (LAC), 2 is the line connection unit 1
(LAI), 3 is a network control device.

The network status signal is received by a network status signal receiving circuit (PRV) 22 and stored in register 1 (REGI) 23. The previously received network status signal is stored in register 2 (R2O3).
It is stored in 24.

Comparator (GOMP) 25 is connected to register 1 (REGl
) 23 and register 2 (R2O3) 24, and if they are different, converter 1 (CONV) 26
to notify.

The conversion circuit 1 (CONV) 26 includes a comparator (COMP
) 25, register 1 (R
A start bit and a stop bit are attached to the contents of EGI) 23 and register 2 (R2O3) 24, and the contents are sent to the serial/parallel conversion circuit (URT') 27 in bit serial form.

In the serial/parallel conversion circuit (URT') 27, the conversion means 1 (C
The signal from ONV) 26 is sent to line connection control unit (LAC) 1 as parallel data.

1) is a block diagram of the principle of the second invention. In the figures, the same reference numerals as in FIG. 1 (al) indicate the same objects.

The line connection unit 2 (LA2) of the second invention includes a network status signal receiving unit (PRV) 22, a conversion means 2 (DEC) 28 for converting changes in the network status signal into a specific character, and a serial/parallel conversion circuit (URT). ') 27.

The network status signal is received by a network status signal receiving circuit (PRV) 22 and entered into a conversion means (DEC) 28.

The conversion means 2 (DEC) 28 generates a specific character corresponding to the state transition when the network state signal changes from the previous one, and converts it into a serial/parallel converter (URT') in a bit serial manner.
27.

The serial/parallel converter (URT') 27 converts this bit serial signal into parallel data and sends it to the line connection controller (LAC).
)1.

[Operation] According to the configuration of the first invention, the network status signal is transmitted bit serially with a start bit and a stop bit attached, so that the same circuit as the serial/parallel conversion circuit (URT) for information signals is used. Line connection control unit (LA) is used as parallel data.
C).

Furthermore, according to the configuration of the second invention, changes in the network state signal are converted into specific characters and sent out as character data using the same circuit as the serial-to-parallel conversion circuit (URT) for information signals. , the line connection control unit (LAC) can receive the network status signal through the same interface as the information data.

In this way, the line connection control unit (LAC) can receive network status signals without using interrupt processing.

[Example] The present invention will be described in more detail below with reference to Examples shown in FIGS. 2 to 5.

FIGS. 2 and 3 show signal transmission systems that are processed by the embodiments shown in FIGS. 4 and 5. FIG.

In the signal transmission systems shown in FIGS. 2 and 3, network status signals are multiplexed with information signals, as shown in the figures.

FIG. 2 is a diagram showing the frame structure of the signal.

In the figure, F indicates a frame bit, B indicates an information bit, and D indicates a control bit.

In this signal transmission system, information bins) B, control bits D, and frame bits F are distributed and arranged, and 20 frames constitute one multiframe.

The control bit D that controls the wire is placed in every frame in the multiframe.

FIG. 3 is a diagram showing the control channel configuration.

In the figure, D indicates the channel number, and the control signals include status display (level) signals LO and L+ for basic control such as call origination, response, and disconnection requests, and selection control (code code) for communication class and dialing. ) signal C.

~C7.

The status display (level) signal is defined not by the values of LO and L+ itself, but by changes in the level status on the receiving side and the received level, and is given meaning such as call origination, response, disconnection request, etc.

FIG. 4 is a circuit diagram of a first embodiment of level signal processing according to the present invention.

Level signal (network status signal) receiving circuit P (not shown)
RV transmits the level signal bit serially to register 1 (R
Transfer to EGI) 23.

23 (REGI) is a register that stores the level signal sent from the level signal receiving circuit (PRV), and 24 (R
2O3) is a register that stores the previously received level signal.

251 is an exclusive OR gate, and a register (REG
I) It inputs the contents L+ of 23 and the contents LI' of register (R2O3) 24, and outputs "1" when the two values are different.

252 is also an exclusive OR gate, and register (REG
I) Inputs the contents Lo of 23 and the contents Lo of register (R2O3) 24, and outputs "1" when the two values are different.

253 is an OR gate, exclusive OR gate 251
or 252 becomes "1", it outputs "1", controls the gate circuit 261, and opens the gate.

262 (SF) is a shift register, which bit-serially transfers the data transferred from the registers (REGI) 23 and (R2O3) 24.

27 (URT') is a serial-to-parallel conversion circuit that converts data transferred bit-serially from the shift register (SF) 262 into parallel data.

When the level signal is received by the level signal receiving circuit (PRV), it is stored in the register (REGI) 23, and the previous level signal stored in the register (REGI) 23 is transferred to the register (R2O3) 24.

The contents of registers (REGl) 23 and (R2O3) 24 are compared by exclusive OR gates 251 and 252, and if they are different, the gate circuit 261 is controlled to change the values of registers (REGI) 23 and (R2O3) 24. is transferred to the shift register (SF) 262.

The first bit of the shift register (SF) 262 always stores a start bit (B+), and the last bit stores a stop bit (B2).
When the transfer from 3 and (R2O3) 24 is completed, serial transfer to the serial/parallel conversion circuit (URT') 27 is started.

The serial-to-parallel conversion circuit (URT') 27 performs serial-to-parallel conversion in an asynchronous mode and transfers parallel data to the line connection control unit (LAC).

FIG. 5 is a circuit diagram of a second embodiment of level signal processing according to the present invention.

In the figure, 23 (REGI), 24 (R2O3)
, 27 (URT") indicate the same components as in FIG.

281 is register (REGI) 23 and (R2O3) 24
It is a comparator that compares the contents of 251°25 in Figure 4.
This can be realized with a configuration similar to that of 2 and 253.

282 is register 1 (REGI) 23 and register 2
This is a decoder that creates a specific character from the value of (R2O3)24.

The level signal received from the communication network is first sent to the register (RE
GI) 23, and the level state before reception is sent to register 2 (R2O3) 24.

The contents of register 1 (REGI) 23 and register 2 (R2
The contents of O3) 24 are compared by a comparator (COMP) 281, and if there is a change, a level signal reception request signal is sent to the line connection control section (LAC).

The decoder (DEC) 282 has register 1 (REG
l) 23 and register 2 (R2O3) 24(7) Converts the value into a predefined character corresponding to the state change, and converts it into a bit serial to serial/parallel converter circuit (URT'
)27.

A serial/parallel conversion circuit (URT") 27 converts the data into parallel data 1 and sends it to the line connection control unit (LAC) using the same interface used for receiving information data.

When the line connection control unit (LAC) receives the level signal reception request signal, the line connection control unit (LAC) receives the level signal in the same process as receiving information data.

[Effects of the Invention] As explained above, according to the present invention, the line connection control unit (L
Since the AC interface is simplified and the burden of interrupt processing is relieved, network control signals can be processed efficiently, and the practical effect is extremely large.

[Brief explanation of drawings]

Figure 1 is a principle block diagram of the present invention. Figure 2 is a diagram showing the frame structure of a signal processed by an embodiment of the present invention. Figure 3 is a channel of a signal processed by an embodiment of the present invention. 4 is a circuit diagram of a first embodiment of level signal processing according to the present invention; FIG. 5 is a circuit diagram of a second embodiment of level signal processing according to the present invention; FIG. 6 is a circuit diagram of a second embodiment of level signal processing according to the present invention. FIG. 7, which is a block diagram of the applied device, is a circuit diagram showing network status signal processing according to the prior art. In the drawing, 1 is a line connection control unit (LAC'), 2 is a line connection unit (LA), 3 is a network control device, 21 is a serial/parallel converter circuit (URT), and 22 is a network control signal receiving circuit (PRV). , 23, 24 are registers (REGl, 2), 25, 281 are comparators (C
26 is the conversion means 1 (CONV), 27 is the serial-to-parallel conversion circuit (URT'), 28 is the conversion means 2 (DEC), 251 and 252 are exclusive OR gates, 253 is an OR gate, 261 is a gate 262 is a shift register (SF), and 282 is a decoder (DEC). (b) Block diagram of the principle of the present invention Fig. 1 Fig. 2 Fig. 3 Fig. 24.
11-) First embodiment circuit diagram of level signal processing according to the present invention No. 6
Figure 7

Claims (3)

[Claims] (1) A serial-to-parallel conversion circuit that converts a bit-serial information signal from a network control device into parallel reception data and sends it to a line connection control unit, and a circuit that generates a parallel reception data processing request to the line connection control unit; In a line control device having a line connection section equipped with a network condition signal receiving circuit for receiving a network condition signal from a network control device, when it is detected that a newly received network condition signal is different from the previous network condition signal, A network control system characterized by being configured to transmit parallel received data. (2) A register (23) that holds the network status signal received by the network status signal receiving circuit, a register (24) that holds the previous network status signal, and the contents of the register (23) and register (24). A comparator (25) that compares and sends out a signal when the contents are different, and a comparator (
25) converting means 1 (26) that adds a start bit and a stop bit to the data in the register (23) and register (24) and sends the data when receiving a signal from the register (25); and converts the bit serial signal into parallel data. Equipped with a serial-to-parallel conversion circuit (27), when there is a change in the network state signal,
The network control system according to claim 1, characterized in that the network status signal is configured to be sent out as parallel data. (3) converting means 2 (28) for converting the network status signal received by the network status signal receiving circuit and the previous network status signal into a predetermined specific character; and a serial/parallel converting means 2 (28) for converting the bit serial signal into parallel data. 2. The network control system according to claim 1, further comprising a conversion circuit (27) and configured to transmit changes in the network status signal as predetermined specific character data.