JPS6362714B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic device with a counter function that includes a plurality of counters that count pulse signals input by operating an external operation switch.

Recently, electronic digital watches, small electronic calculators, etc. have become more and more multi-functional, and some are known to have a counter function with multiple counters that count pulse signals input by operating an external operation switch. There is. This type of counter function is used, for example, as a game score display function by setting game scores on each counter for each individual or team and displaying the contents set on each of these counters. However, this counter function could only be used for simple addition, incrementing the contents of each counter by 1 each time an external operation switch was operated, and its scope of application was extremely narrow. . Therefore, it is conceivable to use an up-down counter as the counter, and to provide a +1 switch and a -1 switch corresponding to each counter, but this has the drawback that the increased number of switches is likely to cause erroneous operation.

The present invention has been made based on the above-mentioned circumstances, and its purpose is to provide an electronic device with a counter function equipped with a plurality of counters, with the function of increasing the contents of the counter by +1 and -1 by operating an external operation switch. An object of the present invention is to provide an electronic device with a counter function that can widen the range of application of the counter function by performing the functions with a small number of switches.

Hereinafter, the present invention will be specifically described based on an embodiment shown in the drawings. FIG. 1 is a circuit diagram of an electronic timepiece to which the present invention is applied. In the figure, reference numeral 1 is an oscillation circuit that generates a reference clock signal;
3 is a frequency dividing circuit that divides the reference clock signal into a 1-second signal, and 3 is a counter circuit that counts the 1-second signal to obtain time information of hours, minutes, and seconds and date information of the month, day, and day of the week. It is. The clock information obtained by the counting circuit 3 is sent to the liquid crystal display section 5 via the gate circuit _G1 and the display switching control circuit 4 in order, and is digitally displayed.

Here, the configuration of the liquid crystal display section 5 will be explained with reference to FIG. This liquid crystal display section 5 displays number display bodies 5A to 5E that display two-digit numbers, character display body 5F that displays the day of the week, and AM/PM.
In addition to AM/PM display, number display 5A to 5D
It has rod-shaped display bodies 5Ga to 5Gd provided correspondingly. In addition, the bar-shaped display bodies 5Ga to 5Gd clearly indicate by their lighting display that the numbers displayed on the corresponding number display bodies 5A to 5D are negative.
Rod-shaped display bodies 5Gb and 5Gd are number display bodies 5A and 5.
Specify the separation between B or 5C and 5D.

Next, referring back to FIG. 1, another circuit configuration will be explained. Symbols S ₁ to _{S 7} are external operation switches that can be operated from outside the watch, and each of these switches S ₁ to _{S 5}
The operation signals of S7 and _S7 are applied to the corresponding one-shot circuits 6-11, causing each one-shot circuit 6-11 to output a one-shot pulse signal. The pulse signal output from the one-shot circuit 6 is applied to a quaternary mode counter 12 which specifies various operation modes, and increments its contents. Each time a pulse signal is input to this mode counter 12 from the one-shot circuit 6, its contents are sequentially incremented as "0", "1", "2", "3", "0", etc. Mode designation signals "0" to "3" corresponding to these contents are output. Note that the mode designation signal "0" is given to the gate circuit _G1 as a gate control signal.

Further, each AND gate 13 to which the mode designation signal "1" is inputted as a gate control signal
Among 21, corresponding one-shot circuits 7 to 10
The operation signal of the switch _S6 is given as a gate control signal via the inverter 22 to the AND gates 13, 15, 17, and 19, into which pulse signals are input. The operation signal of the switch S6 is directly applied as a gate control signal to the AND gates 14, 16, 18, and 20 to which the pulse signal from the switch _S6 is input. Further, a pulse signal from the one-shot circuit 11 is applied to the AND gate 21. The one-shot pulse signals output from the AND gates 13, 15, 17, and 19 are applied to the +1 input terminals of the corresponding up-down counters 23 to 26, and their contents are incremented by +1.
The one-shot pulse signals output from the AND gates 14, 16, 18, and 20 are applied to the -1 input terminals of the corresponding up-down counters 23 to 26, and their contents are incremented to -1, and further,
The one-shot pulse signal outputted from the AND gate 21 is applied to the reset terminal R of each up-down counter 24-27 via a delay circuit 27 to clear its contents. On the other hand, the pulse signal output from the one-shot circuit 11 is applied to an n-ary (for example, decimal) counter 28, and its contents are incremented by +1. The contents of the n-ary counter 28 are incremented by 1 in synchronization with the fall of the input pulse signal.

The contents of the up-down counters 23 to 26 are sequentially sent to the display section 5 via the gate circuit G ₂ to which the mode designation signal "1" is input as a gate control signal and the display switching control circuit 4, and are digitally displayed. In addition, the pulse signal output from the AND gate 21 is sent to the memory section 29 via the gate circuit _G3 , which is input as a gate control signal.

The memory section 29 has a storage capacity of 4 columns and n rows, and each column address is assigned to an up-down counter 23 to
26, and each row address corresponds to the contents of the n-ary counter 28. The pulse signal output from the AND gate 21 is given to this memory section 29 as a read/write signal R/W. When it is "1", it receives a read designation, and when it is "1", it receives a write designation. Further, the contents of the n-ary counter 28 are given to the memory section 29 as address information for specifying a row address via the gate circuit _G4 .
When a write instruction is received, each column of the specified row address has a corresponding up-down counter 2.
3 to 26 are written, and when a read instruction is received, the contents stored in each column of the specified row address are read out in parallel.
The contents read from the memory section 29 are sent to the display section 5 via the gate circuit G ₅ to which the mode designation signal "2" is given as a gate control signal and the display switching circuit 4 in order, and are digitally displayed. Ru. Furthermore, a mode designation signal “3” is given to the memory unit 29 as a read command signal.
While this mode designation signal “3” is input,
All contents stored in the memory section 29 are read out for each column address and sent to the arithmetic section ₃₀ via the gate circuit G6 to which the mode designation signal "3" is given as a gate control signal. , a predetermined calculation is performed.

The arithmetic unit 30 adds and outputs the input contents of the memory unit 29, that is, the contents stored in each row of column addresses, so this arithmetic result data is sent to the display unit 5 via the display switching control circuit 4. is,
Displayed digitally.

The gate circuit _G4 receives a pulse signal and a mode designation signal "2" output from the AND gate 21.
is given as a gate control signal via the OR gate 31, and the contents of the n-ary counter 28 are output from the gate circuit _G4 in synchronization with the timing when the gate circuit _G4 is opened. Furthermore, the contents of the n-ary counter 28 are transmitted to the display section through the gate circuit G ₇ to which the mode designation signals "1" and "2" are given as gate control signals through the OR gate 32 and the display switching control circuit 4. 5 and digitally displayed.

Note that the mode designation signals "0" to "3" are respectively applied to the display switching control circuit 4 as display switching signals.

Next, the display operation of the electronic clock configured as described above and the operation of inputting game scores for each individual or team, for example, will be explained with reference to FIGS. 3 to 6. When the content of the mode counter 12 is set to "0", the gate circuit
G ₁ is opened, and the time information obtained by the clock counting circuit 3 is sent to the display unit 5, and for example, as shown in FIG.
"Seconds" is displayed.

In this normal time display mode, switch S ₁
When operated once, the content of the mode counter 12 is incremented from "0" to "1" and the mode is switched to the game score display mode. That is, mode counter 1
Since the mode designation signal “1” is output from 2,
Gate circuits G ₂ and G ₇ are opened, and the contents of each up-down counter 23 to 26 and the n-ary counter 28 are
For example, as shown in FIG. 4, the score of team A is "-3 points," the score of team B is "-4 points," and the score of team C is "-16 points." ”,
The score of the D team, "23 points", is displayed, and
The number of games "1" is displayed. This display allows each team to know the score results of other teams.

Then, in the game score display mode, when the switch _S7 is operated after checking the score result of the first game, a one-shot pulse signal is output from the AND gate 21, so the gate circuits _G3 and _G4 are opened. At the same time, the memory unit 29 receives a writing designation. Therefore, the memory section 29 stores the contents of each up/down counter 23 to 26 and n.
Since the contents of the base counter 28 are given, the memory unit 29 is designated with a row address corresponding to the contents of the base n counter 28, that is, row address "1", and each column of this row address "1" is assigned a corresponding The contents of the up-down counters 23 to 26 are written. Therefore, the memory unit 29 stores the scores for each team in the first game, as shown in FIG.

Thereafter, a one-shot pulse signal is output from the delay circuit 27, thereby clearing the contents of each up-down counter 23-26.
Further, the n-ary counter 28 is connected to the one-shot circuit 11.
The contents are incremented by +1 in synchronization with the falling edge of the pulse signal output from the pulse signal, and become "2". The result display state is as shown in FIG. 6, and the result of the second game can be entered.

Therefore, when inputting the score result of the second game, in the score display mode of the game, first turn the switch S ₆ depending on whether the score result to be input is a positive value or a negative value. Manipulate. That is, for example, the score result of team A in two games is
If it is "-2 points," operate switch _S6 , and while operating switch _S6 , operate switch _S2 corresponding to the A team twice. As a result, a one-shot pulse signal is output from the AND gate 14 each time the switch _S2 is operated, and is sequentially applied to the -1 input terminal of the up-down counter 23.
is set to "-2", which is the score of the A team. On the other hand, if the A team's score is not a negative value, for example, "+2 points," operate switch S ₂ twice while the operation of switch S ₆ is released (non-operated state). . As a result, a one-shot pulse signal is output from the AND gate 13 every time the switch _S2 is operated, and is applied to the +1 input terminal of the up-down counter 23, so "2" is set in the up-down counter 23. be done. Similarly, when inputting the scores of other teams, teams B to D, if the input score is a negative value, in the operating state of switch _S6 ,
If the switch corresponding to a team among S ₃ to _{S 5} is operated the number of times according to the score of that team, and if the input score is positive, switches S ₃ to S 5 are operated while switch S ₆ is not operated. By operating the switch corresponding to a team out of ₅ the number of times corresponding to the score of that team, the score results of teams B to D can be set in the corresponding up-down counters 23 to 26. Incidentally, as described above, the score result of the second game is displayed on the display section 5, and is also stored in the memory section 29 according to the operation of the switch _S7 .

By performing such an operation every time each game ends, the score results of each game are stored in the memory section 29 for each individual or team.

When the contents of the mode counter 12 are set to "2" by operating the switch _S1 , the score results of each game stored in the memory section 29 can be sequentially displayed. That is, when the content of the mode counter 12 is set to "2", the gate circuits G ₄ and G ₅ are opened and the content of the n-ary counter 28 is provided to the memory section 29 . In this case, when a row address corresponding to the contents of the n-ary counter 28 is specified, the memory section 29 receiving a read instruction reads the contents stored in each column of the specified row address in parallel. gated circuit
It is sent to the display unit ₅ via G5 and displayed. Therefore, each time the switch _S7 is operated to increment the contents of the n-ary counter 28, the row addresses of the memory section 29 are sequentially changed, so that the stored contents are read out and displayed for each row address. . This allows the player to know the results of each game up to that point during the game.

When the final game is finished, by operating the switch _S1 once to set the content of the mode counter 12 to "3", the total score for each individual or team can be displayed. That is, when the mode designation signal "3" is output from the mode counter 12, all the contents stored in the memory section 29 are sequentially read out for each column address, and the contents are read out sequentially for each column address. The signal is sent to the arithmetic unit 30 via the gate circuit _G6 which is opened.
Then, in the calculation section 30, the total score for each individual or team is calculated, and the total score is sent to the display section 5 and sequentially displayed.

In this way, each up/down counter 23-2
The contents of 6 are stored in the memory unit 29 each time each game ends, so during the game, the results of each game up to that point can be read out and displayed, and after the final game is over, the results of each game up to that point can be read out and displayed. It is possible to read the score results of each game for each individual or team from the memory section 29, and calculate and display the total score for each individual or team in the calculation section 30.

In addition to simple addition counting, it is also possible to count subtraction, so for example, in addition to counting the scores of games that involve subtraction, when correcting the values set in the up-down counters 23 to 26, , the correction operation can be easily performed. Furthermore, by operating any of the switches _S2 to S6 when the switch _S6 is not operated or when the switch _S6 is operated, a desired counter among the up-down counters performs addition or subtraction. Operation becomes extremely easy.

FIG. 7 shows the configuration of a display unit according to another embodiment of the present invention. In this embodiment, seven dots displaying the days of the week are used together to display the number of games played. This is what I did. With this configuration, it is possible to easily distinguish between the score display and the game count display.

In the above embodiment, a plurality of switches _S2 to _S5 are provided corresponding to the up-down counters 23-26, but each up-down counter 23-26 can be selectively designated by one switch. In addition, the specified up-down counter may be added or subtracted by operating an addition or subtraction switch.

Furthermore, if the game time is limited, a second display or a day of the week display may be used in combination to display the elapsed time or decreased time of the game.

Furthermore, the present invention can be used for purposes other than the game score display function, and can be applied to electronic devices other than electronic watches.

As explained in detail above, the present invention enables pulse signals to be input by operating an external operation switch.
In an electronic device with a counter function that has multiple counters that count by 1, by providing a function to subtract the contents of the counter by -1 by operating an external operation switch, it is possible to perform not only addition counts but also subtraction counts. For example,
The range of applications of the counter function can be expanded, such as counting the score of a game that involves subtraction, and even if the count value is set incorrectly, it is easy to correct it.

[Brief explanation of drawings]

1 to 6 show an embodiment of the present invention, in which FIG. 1 is a circuit diagram of an electronic timepiece to which this invention is applied, FIG. 2 is a diagram of a display section, and FIG.
Figures 4 and 6 are diagrams showing display states, and Figure 5.
The figure shows the contents of the memory section, and FIG. 7 is a configuration diagram showing the display section of an electronic timepiece according to another embodiment of the present invention. 12...Mode counter, 13-21...AND gate, 23-26...Up-down counter, _S2 - _S7 ...External operation switch.

Claims (1)

[Claims] 1. A plurality of operation switches S2, S3, S4, S5
and a plurality of counting means 23, 24, 25, 26 provided corresponding to each of the plurality of operation switches.
a single operation switch S6 provided separately from the plurality of operation switches; and addition control that causes the corresponding counting means to perform addition by a predetermined number by operating one of the plurality of operation switches singly. Means 13, 15, 17, 1
9; and subtraction control means 14, 16, 18, 20 for causing the corresponding counting means to subtract a predetermined number by operating one of the plurality of operation switches simultaneously with the single operation switch; a memory means 29 capable of storing a plurality of contents of each counting means; a calculating means 30 for calculating total value data by calculating a plurality of contents of each counting means stored in the memory means; An electronic device with a counter function, comprising display means 4 and 5 for displaying the obtained total value data.