JPS6367775A - semiconductor equipment - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a lateral transistor, in particular a current amplification factor (
Hereinafter referred to as % hFK. ) and has excellent noise characteristics.

[Conventional technology]

NPN ) transistors and P in bipolar integrated circuits
The mixed use of NP) transistors has advantages such as increased freedom in design and simplification of circuit configuration. Generally, horizontal PN
P) transistors are well known. Horizontal PNP)
The transistor is usually fabricated by simultaneously forming an emitter region 4 and a collector region 5, as shown in a schematic cross section in FIG. 2, by utilizing the pace diffusion of a vertical NPN transistor.

[Problems that the invention helps solve]

In the lateral transistor shown in FIG. 2, most of the carriers injected from the emitter region 4 are conducted through the substrate surface.
It will flow into the collector region 5. Since the substrate surface is directly under the oxide film, many interface states remain due to the oxide film, a thermal strain layer generated during the heat treatment process, uneven distribution of impurities, etc.

Such an interface state promotes trapping, re-emission, and recombination of carriers conducted on the substrate surface.

According to the former, the collector current fluctuates and the noise characteristics deteriorate, and according to the latter, the base current increases and hFE decreases. Furthermore, since it is difficult to control the interface states on this surface during the fabrication process, there is a drawback that it is difficult to suppress noise characteristics and variations in hFE.

[Means for solving problems]

In order to eliminate such drawbacks, the present invention is an improvement in that the carriers injected from the emitter region do not conduct across the substrate surface, but conduct within the substrate. That is, the present invention has two formed emitter and collector regions where the effective base width of the transistor is always defined within the bulk.

〔Example〕

The non-invention will be explained below with reference to the drawings.

FIG. 1 is a schematic cross-sectional view of a lateral PNP transistor according to an embodiment of the present invention. The same parts as in the conventional example shown in FIG. 2 are given the same numbers. Similarly, the electrodes and the openings in the oxide film are omitted.

In this embodiment, an emitter region 8 and a collector region 9 are laterally spaced apart and formed on an N-type buried layer. Further, on the surface of the N-type epitaxial layer, an emitter region 10 and a collector region 11 are formed, respectively.
They are formed spaced apart laterally so as to be in contact with the upper part of the The distance between emitter region 8 and collector region 9 is shorter than the distance between emitter region 10 and collector region 11.

〔Effect of the invention〕

As explained above, according to the present invention, carriers injected from the emitter region do not conduct through the substrate surface but conduct inside the substrate, so that they are not affected by the interface states distributed on the substrate surface. . Therefore, compared to a conventional horizontal PNP transistor, a higher hFE can be obtained, and the noise characteristics are also significantly improved. The present invention can be realized without making any changes to conventional processes.

However, the present invention is not limited to the above embodiments, and even if the polarity is changed, the scope of the present invention does not depart from the scope of the present invention.

[Brief explanation of drawings]

FIG. 1 is a schematic sectional view showing an embodiment of a semiconductor device according to the present invention, and FIG. 2 is a schematic sectional view showing an example of a conventional semiconductor device. DESCRIPTION OF SYMBOLS 1... P-type silicon substrate, 2... N-type high concentration buried region, 3... N-type epitaxial layer, 4... Pfi emitter region, 5... P-type collector region, 6...・N-type base electrode extraction region, 7... silicon oxide film, 8
... P-type emitter region, 9... P-type collector region,
10...P-type emitter region, 11...P-type collector region. Agent: Susumu Uchihara, patent attorney:
'-;, $ 1 Figure 2

Claims (1)

[Claims] a semiconductor layer of an opposite conductivity type formed on a semiconductor substrate of one conductivity type; a first region of the opposite conductivity type embedded between the semiconductor layer and the semiconductor substrate; and a first region of the opposite conductivity type. and the second region of one conductivity type embedded between the semiconductor layer and the semiconductor layer;
a third region of one conductivity type that is laterally spaced apart from the second region and embedded between the first region and the semiconductor layer; a fourth region of one conductivity type formed so as to be in contact with an upper part of the region; and a fourth region of one conductivity type formed on the semiconductor surface so as to be in contact with an upper part of the third region and spaced laterally from the fourth region. the fifth region of the one conductivity type formed, and the distance between the second region and the third region is shorter than the distance between the fourth region and the fifth region. A semiconductor device characterized by: