JPS637015A - Pulse generator - Google Patents

Abstract

PURPOSE:To generate a pulse signal with high resolution, high stability and very large variable range of pulse width by forming a pulse whose period is an integral multiple of the period of a reference clock, forming a fractional pulse with high resolution and summing both pulses. CONSTITUTION:In setting a desired pulse width T, a CPU 18 immediately calculates values N, tx in an equation of T=Nt0+tx (where t0 is a period of the reference clock, N is the number of reference clocks, and tx is the width of a fractional pulse). The pulse width Nt0 is obtained accurately by multiplying the reference clock by N. Further, a digital signal s2 representing the width tx of the fractional pulse is outputted from the CPU 18 and subject to DA conversion or the like by a fractional pulse generator 20, from which a signal s3 whose pulse width is tx is outputted. Then a desired pulse width T is obtained by synthesizing the values Nt0 and tx.

Description

[Detailed description of the invention] B. “Purpose of the invention” (Industrial application field) The present invention relates to improvements in pulse generators.

[Conventional technology]

The following two methods are known for controlling the pulse width in a pulse generator.

(a) A method of creating a ramp (ran+p) waveform and creating a pulse by converging this with a - constant voltage.

In this case, the pulse width can be set by changing the level of the constant voltage.

(B) A method that creates arbitrary pulse widths by dividing the reference clock.

[Problem that the invention seeks to solve]

However, the above method has the following problems.

Method (a) is difficult because it requires extremely high stability of the lamp generator, etc. in order to reduce pulse width fluctuations and set the pulse width with high resolution. There is also the problem that resolution deteriorates as the pulse width improves.

Method (B) is! i! Since a quasi-clock is used,
Although it can produce a stable signal with a good pulse width, the problem is that the resolution is limited to 1J by the period of the reference clock.

An object of the present invention is to provide a pulse generator that can output a signal with high resolution and a stable pulse width.

``Structure of the Invention'' (Means for Solving the Problems) The present invention provides an integral multiple of the period of the reference clock in order to obtain an output signal with a pulse width T set in order to solve the above problems. a CPU that outputs a signal (sl) representing a fractional pulse width and a signal @ (82) representing a fractional pulse width; a control circuit that generates a pulse width signal (s3) that outputs a pulse width signal (s3) corresponding to the fractional pulse width according to the signal (s2); Feedback means for changing the voltage and feeding back a signal based on the voltage to the CPU, and combining the output signal (B) of the control circuit and the output signal (s3) of the fractional pulse generator to generate a set pulse width. This device includes a means for outputting a signal of T, and a means for outputting a signal of T.

(Example) Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a diagram showing an embodiment of the present invention.

In the figure, 11 is a time/voltage converter that receives a pulse signal and outputs a signal whose voltage changes depending on the pulse width.

12 is a ΔD converter that converts the output j of the time/voltage converter 11 into a digital signal.

13 responds to a signal S2 introduced from the CPU, which will be described later.
D outputs analog voltage Vχ corresponding to fractional pulse width
There is an A transformer.

14 is a delay line whose delay time is changed by an external control voltage Vχ. This delay line 14 is generally composed of an inductor and a variable capacitance diode (varactor diode).

15 introduces a reference clock (period io) and a signal S1 from the CPU, which will be described later, and sends a signal C with a pulse width to to the variable delay line 14, and outputs a pulse with an integral multiple of the period of the reference clock to the output gate circuit 17. This is a control circuit that sends out a width signal B.

A gate circuit 16 superimposes the output of the delay line 14 and the signal C from the control circuit 15.

Reference numeral 17 denotes a gate circuit that superimposes a pulse width signal (B) having an integral multiple of the period of the reference clock, which is the output of the control circuit 15, and a pulse width signal (s3) corresponding to the fractional pulse width, which is the output of the gate circuit 16. It is.

18 is a CPU that outputs a signal (sl) representing an integral multiple of the period of the reference clock and a signal (s2) representing a fractional pulse width in order to obtain an output signal with a set pulse width T;
(central processing unit
). That is, taking the set pulse width T as T-N-t(,+tx, CP Ll 1
B calculates N and tx, and sends signals s1. s2
This outputs the following.

In addition, the above-mentioned ODA converter 13 and variable delay line 1
4 and the gate circuit 16 constitute a fractional pulse generator 20 surrounded by a dotted line. This fractional pulse generator 20 is a CPU
Any configuration may be used as long as it has the function of introducing the signal δ2 representing the fractional pulse width from 18 and outputting the pulse width signal S3 corresponding to the fractional pulse width.

The operation of the apparatus shown in FIG. 1 constructed as above will be explained with reference to FIG. 2. Fig. 2 is a time chart of the signals of the equipment stand in Fig. 1, and the signal names A, B, etc. written in the drawing of Fig. 1 match the symbols on the left end of Fig. 2. .

First, the present invention will be explained in detail. In the present invention, in order to obtain a desired pulse width T, this pulse width T is decomposed as shown in equation (1).

T=Nto+tx (+>t
o = Period of reference clock (see Figure 2A) N:! ! Quasi-clock number tχ: Fractional pulse width Once the desired pulse width T is set, the CPU 18 can immediately calculate N and tχ in equation (1).

The pulse width Nio can be accurately obtained by multiplying the reference clock by N.

Further, the CPU 18 outputs a digital signal S2 representing the fractional pulse width tx, which is subjected to DA conversion etc. in the fractional pulse generator 20 to output a signal S3 having a pulse width t'x. The desired pulse width T is then obtained by combining Njo and tχ.

However, in reality, depending on the set pulse width 1, the fractional pulse width tχ may be extremely small (tχbo>). However, it is difficult to create a pulse with an extremely small pulse width.

Therefore, the fractional pulse width is (tx+'t.),
Further, the following explanation will be made assuming that a pulse width of (N-1)·to is created as a pulse width that is an integral multiple of the period of the reference clock.

In FIG. 1, a pulse corresponding to (If-1)·to is created by a frequency dividing circuit (not shown) in the control circuit 15, and a pulse corresponding to (1o+1χ) is created by the variable delay line 14 and gate circuit 16. (Figure 2B.

See D>.

For example, a pulse of T=118 ns is used as the reference clock t
When creating with o=10ns, (N-1)・t.

-100ns frequency dividing circuit (inside control circuit 15)
8 ns is created using the variable delay line 14, and 18 ns is obtained at the output of the gate circuit.

Note that in reality, the fractional pulse width may not reach the desired value (1o+1χ) due to the influence of temperature fluctuations, etc., so this fractional pulse is converted into voltage by the time/voltage converter 11, and this voltage signal is converted into a digital signal. Convert to signal and CP LJ
I'm trying to return to 18.

In CP Ll 18, the introduced time/voltage converter 11
The fractional pulse generator 200 adds lli calculation to the signal from
Read the actual output fractional pulse width and adjust C so that the fractional pulse width actually output is exactly (jo+jX>).
By correcting the signal S2 at P U 18 and outputting it again to the DA converter 13, the desired pulse width T is accurately obtained. In addition, with cpuig, time/voltage converter 11
The calculation method for determining the actual fractional pulse width based on the signal from the is described in the patent application filed by the present applicant on June 24, 1986, 1 Hour Measuring Apparatus J.

Also, the control circuit 15 outputs the pulse widths to and 2io and applies them to the time/voltage converter 11 (at this time, the delay amount of the variable delay line 14 may be set to 0 and the pulse widths are applied through the gate circuit 1G). For example, a multiplexer (
(not shown) may be added by switching with the output of the gate circuit 1G), read the voltage value at that time, and use that value as a reference to calculate ■χ by linear interpolation. Precision output is possible.

Furthermore, by sequentially changing the output of the DA converter 13, reading the pulse width value at that time with the AD converter 12, and examining the characteristics of Vx and pulse width, the variable delay line 1
Even if the characteristic No. 4 is not linear, the desired pulse width can be output immediately.

FIG. 3 shows a modification of the present invention, with AD modification 1 of FIG. 1! j
The iB 12 is composed of an A converter 13 and a comparator 30. According to FIG. 3, it has a cylindrical configuration. However, since AD conversion is performed using a successive approximation method using a DA converter and a comparator, it takes time to read the pulse width.

FIG. 4 is a diagram showing a specific example of the configuration of the time/voltage converter 11. In the figure, 41 is an RS flip 70 tube, 42 is a delay line, 43.46 is a constant current source, -10=44, 45 is a current switch, 47 is an integrating capacitor, 48 is a clamp diode, and 49 is a It is a buffer amplifier. According to the time/voltage converter having such a configuration, the pulse width of the signal applied to the terminal p2 is changed to the terminal voltage of the capacitor 47. The operation of the device shown in Fig. 4 is described in detail in the patent application filed by the present applicant on June 24, 1986 titled ``One Hour Measuring Apparatus'', so the explanation of its operation will be omitted in Honkawa at. .

C.E. Effects of the present invention As described above, according to the present invention, a pulse with an integer multiple of the period of the reference clock is created, and a high-resolution fractional pulse is added to this pulse, so the high-resolution and high-resolution pulse is added. It is possible to generate a stable pulse signal with a very wide variable range of pulse width.

Furthermore, since fractional pulses are generated using a time/voltage converter, high-speed and highly stable pulses can be generated. In addition, the delay line is controlled by the DA
Since this is done directly by the transducer, it is possible to output the desired pulses at a higher speed, and it also has the effect of making it easier to correct moisture fluctuations, non-linearity of the delay line, etc.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of the configuration of a pulse generator according to the present invention,
2 is a time chart of each signal of the device shown in FIG. 1, FIG. 3 is a diagram showing a modification of the device shown in FIG. 1, and FIG. 4 is a diagram showing an example of the configuration of a time/voltage converter. 11... Time/voltage converter, 12... AD converter,
13... OA converter, 14... Variable delay line, 15... Control circuit, 16.17... Gate circuit, 18... CPIJ, 20... Fractional pulse generator.

Claims (1)

[Scope of Claims] A CPU that outputs a signal (s1) representing an integral multiple of the period of a reference clock and a signal (s2) representing a fractional pulse width in order to obtain an output signal with a set pulse width T; a control circuit that introduces the signal (s1) and a reference clock and creates a pulse width signal (B) having an integral multiple of the period of the reference clock; and a pulse width signal corresponding to a fractional pulse width according to the signal (s2). (s3); a feedback means for changing the voltage according to the pulse width of the output signal of the fraction pulse generator and feeding back a signal based on the voltage to the CPU; and an output signal of the control circuit. (B) and an output signal (s3) of the fractional pulse generator, and means for outputting a signal with a set pulse width T.