JPS6372000A - Semiconductor memory circuit - Google Patents

Abstract

PURPOSE:To reduce a semiconductor chip area by providing a horizontal group decoder and a vertical group decoder in an array and adding an OR circuit. CONSTITUTION:The titled circuit is consisting of the horizontal group decoder 1 having the input of a high order column address 10 and the output of a horizontal group selection signal 12, a vertical group decoder 2 having the input of a low order column address 11 and the output of a vertical group selection signal 13, a horizontal group selection circuit 4 having the input of the horizontal group selection signal 12 and outputting the data of a bit line 3 to a horizontal group data output line 15, a vertical group selection circuit 5 having the input of the vertical group selection signal 13 and outputting the data of the bit line 3 to a vertical group data output line 16, the OR circuit 6 having the input of the horizontal group and the vertical group selection signals 12, 13 and the output of a bit line selection signal 14 and a switch 7 for connecting the bit line 3 and a data input/output signal line 17 by the bit line selection signal 14. The column address is divided into two sets and first and second decoders 1, 2 and the OR circuit are provided in the array, thereby, the number of wirings passing through the array is deleted and the semiconductor chip area can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory circuit, and more particularly to a semiconductor memory in which horizontal/vertical parity and ECC circuits are arranged on the same substrate.

[Prior Art] Semiconductor Memory a) In order to improve errors in software 1 and improve yield, a semiconductor memory in which an ECC circuit is turned on is effective. 1. In ν, the horizontal/vertical parity method E
).

An example of an ECC enclosure using the conventional horizontal/vertical parity method is shown in the block diagram of FIG. In this conventional example, the circuit for selecting horizontal group data and vertical group data and sending it to the valid generation circuit is a decoder that receives a column address as a peripheral circuit and outputs a horizontal group selection signal and a vertical group j2 selection signal. 1, 2, and a 1 selection circuit that outputs the horizontal group selection signal or the vertical 1'3 selection signal 3 in the array and outputs the data on the bit line 3 to the horizontal I':f, data output line or vertical group data output line.・l, 5
It consists of Furthermore, within the array, a decoder 8 is required to input the column address manually and output the pin I-line j7 signal number, and a switch 7 connects the pin 1 to line 3 and the data output signal line using the bit line selection signal. be.

[Problem that the invention seeks to solve]

In a series of conventional circuits, column addresses, horizontal group and vertical group selection signals, horizontal group and vertical group data output lines, data input/output signal lines, etc. are required as wiring that runs through the array. The disadvantage is that the chip area is significantly increased compared to a semiconductor memory that does not have a circuit.

An object of the present invention is to solve such problems, to provide a horizontal group decoder and a vertical group decoder in an array, and to provide horizontal group and vertical group jx selection signals that pass through the inside of the array. It is an object of the present invention to provide a semiconductor memory circuit in which a column decoder is removed and the semiconductor chip area is reduced by adding an OR circuit.

[Means for Solving the Problems-1] The configuration of the present invention provides a semiconductor memory circuit in which horizontal and vertical parity and error correction circuits are arranged on the same substrate.
first and second decoders which divide column addresses into two sets, upper and lower, and manually input address signals belonging to each set, and output respective selection signals for the flat group and vertical group to 7;
It is characterized by comprising an OR circuit which inputs the output signals of each of these decoders and outputs the bit line jX signal signals respectively.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention. In this embodiment, a horizontal group decoder 1 receives an upper column address 10 and outputs a horizontal group selection signal 12; a vertical group decoder 2 receives a lower column address 11 and outputs a vertical group selection signal 13; Horizontal group selection signal 12
Input the data on bit line 3 to horizontal group data output line 1
5, the horizontal group selection circuit 4 and the vertical group selection signal 13 output to
A vertical group selection circuit 5 inputs the bit line 3 and outputs the data of the bit line 3 to the vertical 1:゛r data output line 16, and a vertical group selection circuit 5 which inputs the horizontal 1 (゛) and the vertical group selection signal 12. An OR circuit 6 which outputs the signal 14, and a
It is composed of a switch 7 that connects the pin line 3 and the data input/output signal line 17 in response to a line selection signal 14.

Next, the operation of this circuit will be explained.

The horizontal group and vertical group decoders 1, 2 output horizontal group or vertical group selection signals 12.13, and these horizontal group and vertical group selection signals 12.13 are transmitted to the respective 3π selection circuits! 1.5 to output the data on the pin 1-line 3 to the horizontal group and vertical group data output lines 15 and 16. On the other hand, the OR circuit 6 is driven by the horizontal group and vertical H'f selection signals 12 and 13 and outputs the bit line selection signal 1/1. Further, the switch 7 connects the pin I-line 3 and the data input/output signal line 17 according to the bit line selection signal 14. FIG. 2 is a block diagram showing a second embodiment of the present invention.

A plurality of horizontal group decoders with the same upper column address input are represented by the horizontal B't decoder 1 of 1-), and the output of this horizontal group decoder 1, the horizontal group m option A 3, is divided into two horizontal The group jA selection multiplication signal 21.degree. 122 is input to the Mizuko 0 selection circuit 41.42 and the OR circuit 61.62. Although two systems are shown in the other (j), each system is the same as in the first embodiment. That is, vertical group decoders 21, 22, bit lines 31, 32, vertical group selection circuit 51
, 52. Bit line, data input/output signal line Sui Sochi 71
．． 72 has two systems. This embodiment has the advantage that the number of decoders can be reduced because the horizontal group decoder 1 is used in common.

1. Effects of the Invention] As shown in the embodiments above, the present invention divides the column addresses into two sets and includes a first decoder 1 and a second decoder 1 in the array.
, 2 and an OR circuit, the inside of the array is
This has the effect of reducing the number of wires passing through and reducing the area of the semiconductor chip.

[Brief explanation of the drawing]

1 and 2 are block diagrams of the first and second implementations of the present invention, and FIG. 3 is a block diagram of a conventional horizontal group and a circuit that selects immediately preceding data. 1.・Horizontal group decoder, 2, 21.22... Vertical group decoder, 3, 31.32... Pitch 1 to line, 4° 41
．． 42...Horizontal group 1u selection circuit, 5,51.52...
Vertical group selection circuit, 6, 61.62...OR circuit, 8
...Column address decoder, 7, 71.72...
Pill line/data input/output signal line switch, 9... Column address, 10... Upper column address, 11...
・Lower column address, 1.2, 121, 122...
・Horizontal group selection signal, 13, 131, 132... Vertical group selection circuit, 14, 141, 142... Pin 1 to line 3M
Selection (No. 8, 15, 1.51.152...Horizontal group data output line, 16, 161, 162...Vertical group data output line, 17, L71, 172...Data input/output signal line, ' -8J

Claims (1)

[Claims] In a semiconductor memory circuit in which horizontal and vertical parity and error correction circuits are arranged on the same substrate, column addresses are divided into two groups, upper and lower, and address signals belonging to each group are inputted, and each selection signal for the horizontal group and vertical group is input. What is claimed is: 1. A semiconductor memory circuit comprising: first and second decoders that output a bit line selection signal; and an OR circuit that receives an output signal from each of these decoders and outputs a bit line selection signal.