JPH03230622A - Decoding semiconductor device - Google Patents

Abstract

PURPOSE:To save the area of a semiconductor device shared on a semiconductor integrated circuit by providing a small-sized 2nd decoding circuit group converting only an address and a data into parallel from a serial state to a single 1st decode circuit. CONSTITUTION:A 1st decoding circuit 31 is provided with the small-sized 2nd decoding circuit groups 37-39, which are connected to an address output signal line 35 and a data output signal line 36 for the data signal synchronously with the address signal. That is, the single decode means is enough for a single device and the 2nd decoding means generate a parallel signal by an address signal and a data signal, which are realized with small scale circuits and they are arranged in the vicinity of controlled circuit block groups 17-19. Thus, the area of the semiconductor device occupied on the semiconductor integrated circuit is decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a decoding semiconductor device that decodes serial data into parallel data.

2. Description of the Related Art A conventional decoding semiconductor device inputs at least a serial control signal, a serial data signal, and a clock signal synchronized with the serial control signal and the serial data signal, and decodes a data signal obtained by decoding the serial data signal. It consists of a decoding circuit that outputs. FIG. 2 shows the configuration of a conventional decoding semiconductor device.

In Figures 2(a) and (b), 1.2.3.4 is
The decoding circuit inputs a serial control signal, a serial data signal, and a clock signal synchronized with the serial control signal and the serial data signal, and outputs a data signal obtained by decoding the serial data signal. 5.
6.7.8 is the input signal line for the serial control signal; 9.
10.11.12 is an input signal line for the serial data signal, 13 is an input signal line for the synchronized clock signal, 1
4, 15, and 16 are output signal lines for the decoded data signals. 17, 18, and 19 are a group of circuit blocks to be controlled.

In the conventional example shown in FIG. Based on the clock signal,
A data signal obtained by decoding the serial data signal is outputted to the output wiring 14, 15, 16 to control the circuit block group 17, 18, 19.

Further, in the conventional example shown in FIG. 2B, the circuit block group 17, 18, 19 to be controlled includes a plurality of the decode circuits 2.
3.4 are arranged respectively.

Problems to be Solved by the Invention However, in such conventional semiconductor devices,
) type, the output signal lines for the decoded parallel data signal are wired from the decode circuit l to the circuit block group 17, 18, and 19, so that these parallel data output wires are connected to a monolithic semiconductor integrated circuit. The area occupied by the circuit-L increases.

Further, the type shown in FIG. 3(b) has a problem in that a plurality of large-scale decoding circuits 2, 3, and 4 are required.

The present invention solves the above problems of conventional decoding semiconductor devices, and aims to provide a decoding semiconductor device in which the semiconductor device occupies a small area on a semiconductor integrated circuit.

Means for Solving the Problems The present invention receives at least a serial control signal, a serial data signal, and a clock signal synchronized with the serial control signal and the serial data signal, and provides an address signal and a data signal synchronized with the address signal. and a second decoding means that decodes the data signal based on the address signal.

Effect: With this configuration, the first decoding means can be used alone. Furthermore, the second decoding means can be a small-scale circuit that generates a parallel signal from the address signal and the data signal, and can be placed near the group of circuit blocks to be controlled. Wiring is the shortest possible.

EXAMPLES Hereinafter, examples of the present invention will be described with reference to the drawings.

FIG. 1 shows a decoat semiconductor device which is an embodiment of the present invention.

31 is a serial control signal, a serial data signal,
a first decoding circuit as an example of a first decoding means that inputs the serial control signal and a clock signal synchronized with the serial data signal and outputs an address signal and a data signal synchronized with the address signal; 3 is an input signal line for the serial control signal, 33 is an input signal line for the serial data signal, 34 is an input signal line for a clock signal connected to the serial control signal and the serial data signal, and 35 is an output signal for the address signal. line, 36
is an output signal line for a data signal that is similar to the address signal. Further, 37.38.39 is a second decoding circuit group as an example of a second decoding means that is synchronized with the clock signal and decodes the data signal based on the address signal, and I4.15.16 is a second decoding circuit group as an example of the Output signal lines 17, 18, and 19 for decoded data signals are a group of circuit blocks to be controlled. The above-mentioned σtsuku signal input line 34,
Address signal output line 35 and data output line 36 are connected to second decoding circuit group 37, 38, and 39, respectively. Note that the output signal line 35 for each address signal and the output signal line 36 for the data signal are partially shared.

Next, the operation of the above embodiment will be explained.

First, the serial control signal is input to the first decoding circuit 31 from the input signal line 32, the serial data signal is input from the input signal line 33, and the clock signal is input from the input signal line 34.

The first decoding circuit 31 outputs the address signal from the output signal line 35 and a data signal synchronized with the address signal from the output signal line 36, and the second decoding circuit group 37.3 This is the input to 39.

Next, the second decoding circuit group 37, 38, 39 synchronized with the clock signal 34 outputs a data signal synchronized with the address signal based on the address signal output from the first decoding circuit 31. It is decoded and output from output signal lines 14, 15, and 16 to control the circuit block group 17, 18, and 19.

Hereinafter, as indicated by L, according to this embodiment, the first decode circuit 31 is connected to the output signal line 35 of the address signal and the output signal line 36 of the data signal connected to the address signal. In addition, a small-scale second decoding circuit 3
By providing the 7.38.39 groups, the area occupied by the monolithic semiconductor device in the semiconductor integrated circuit t can be reduced. Further, the second decoding circuit group is connected to the first decoding circuit by sharing a wiring for outputting the address signal and a wiring for outputting a data signal synchronized with the address signal. Therefore, the areas of the address signal output wiring and the data signal output wiring are reduced.

As is clear from the detailed description of the invention, the first decoding circuit is a single unit, and the second decoding circuit group is also a small-scale circuit that only converts an address decoder and data from serial to parallel. Since the semiconductor device can be placed near the group of circuit blocks to be controlled, it is possible to significantly reduce the area occupied by the semiconductor device on the semiconductor integrated circuit.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a decoding semiconductor device according to an embodiment of the present invention, and FIGS. 2(a) and 2(b) are block diagrams showing the configuration of a conventional decoding semiconductor device, respectively. 1.2.3.4...Conventional decoding circuit, 5.6.7
．． 8.32...Input signal line for serial control signal, 9.
10, 11.12.33... Input signal line for serial data signal, 13.34... Input signal line for clock signal synchronized with the serial control signal and the serial data signal, 14.15.16... - Output signal line for the signal obtained by decoding the data signal, 17.18.19...Circuit block group, 35...Output signal line for the address signal, 3
6... Output signal line for a data signal synchronized with the address signal, 37.38.39... Second decoding circuit group.

Claims (2)

[Claims] (1) A first decoder that inputs at least a serial control signal, a serial data signal, and a clock signal synchronized with the serial control signal and the serial data signal, and outputs an address signal and a data signal synchronized with the address signal. and second decoding means for decoding the data signal based on the address signal. (2) The decoding semiconductor device according to claim 1, wherein the first decoding means and the second decoding means are located on the same monolithic semiconductor integrated circuit and operate with the same clock.