JPS6374094A - Display device - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a display device in which display elements constituting the display device are connected in a box-like manner, and specifically relates to the flicker period thereof.

[Conventional technology 1] Conventionally, in a display device that uses a large number of display elements to display the status of various types of discriminators, processing results, etc., in order to save the power consumption of the display elements, a large number of display elements are used. In many cases, the display elements are connected in a matrix of n columns and n rows, and each display element is time-divisionally driven row by row.

Therefore, in such a display device, conventionally, in addition to a display in which m×n display elements are connected in a matrix of m columns and n rows, a decoder that outputs a timing signal instructing the display timing of each row, A place to set display signals for turning on or off for m×n display elements J! ! ! a control circuit that inputs an encoder (No. 8) representing the display timing of each row to the decoder, and supplies a lζ display signal set from the processing circuit to the display unit row by row in synchronization with the display timing of each row. A circuit is provided, and the m×n display elements are turned on or off simultaneously in units of milligrams, and are configured to turn on or off on an hourly basis uO in units of rows.

By the way, in such a display device, when it becomes necessary to blink (flicker) any display element among the m×n display elements at a predetermined period, the processing circuit measures the flicker period, and the control circuit also measures the flicker period. The display signal of the corresponding display element set to 1 is switched to a ``light on'' or ``light off'' signal at the flicker period.

[Problems to be Solved by the Invention] However, when flicker control is performed on an arbitrary display element as described above, the processing circuit performs the following processes: 1. Measuring the flicker period, and 2. Setting the switching of the display signal for the corresponding display element. This increases the burden on the processing circuit and reduces the throughput of processes other than display control.

An object of the present invention is to provide a display device that can perform flicker control of display elements without increasing the burden on processing circuits.

[Means for solving the problem] The present invention outputs a flicker signal to an arbitrary display element among m×n display elements from a processing circuit, and
A register that stores the flicker signal in units of rows and outputs the flicker signal in units of rows according to an encode signal output from the control circuit, and a first gate that outputs the flicker signals in units of rows output from the register at a desired flicker period. and a second gate circuit that outputs an AND signal of the output signal of the first gate circuit and the display signal output from the control circuit as a display signal to a display device, and the processing circuit eliminates flickering. The display element is configured to blink a display element to which a signal is set at a desired flicker cycle.

[The flicker signal of any display element to be caused to flicker is set and stored in the action register from the processing circuit. This flicker signal is read out row by row by an encode signal output from the control circuit, and output at a desired flicker period via the first gate circuit. Then, by calculating the logical product of the output signal of the first gate circuit and the display signal for the corresponding display element in the second gate circuit, if the display signal is "lit", the display signal of "the lamp is lit" is determined. A desired flicker cycle is switched between "off" and "on" states according to the flicker signal and is input to the display.

This allows any display element to blink at a desired flicker cycle.

Therefore, the processing circuit only needs to set the flicker signal of the flicker display element in the register, which reduces the burden on the processing circuit.

[Example code] FIG. 1 is a circuit diagram showing an embodiment of the present invention.

In the figure, 1 is m=6. n-8 combination of 148 display elements LD11 to LD16. . . . Shi[) 81 to Shi [) 86 are connected in a matrix of 6 columns and 8 rows to form an lζ display. 2 outputs timing signals SC1 to SC8 for instructing the display timing for the display elements in each row, and transistor Q1 〜Q8 to connect the display elements of each row to l<
f4 is the first decoder; 3 is a processing circuit that sets display signals for turning on or off and flicker signals for 6×8 display elements; 4 is +ij; a 3-bit encoder that represents the display timing of each row for the decoder 2; Signal So, 3
1. 5 is a control circuit that inputs S2 and outputs the display signal set from the processing circuit 3 as DLI to DL6 for each row in synchronization with the display timing of each row; Flicker signal DTO~
a register 6 that stores the flicker signal DTO-DT6 and outputs the stored flicker signal DTO-DT6 as signals FDLI-FD1G in row units by inputting the encode signals SO-S2 outputted from the control circuit 4 as read address signals; 8 is an oscillator that generates a clock signal CLK with a predetermined period; 7 is a frequency dividing circuit that divides the clock signal CLK and outputs a flicker period signal FT with a desired period; A first gate circuit which outputs the flicker signals FDL1 to FDL13 outputted from the register 5 at the cycle of the flicker period signal FT; 9 consists of Nant gates G7 to G12, and the output signal of the first gate circuit and control Display signal DL1~ output from circuit 4
Obtain the AND signal with D[-6 and display column I! of display 1. +1
Drive! This is a second gate circuit that is input in parallel to the Fll line.

In the above configuration, the processing circuit 3 sets a display signal of "4111" to the control circuit 4 for the display element to be turned on among the 6×8@ display elements, and "OPI" for the display element to be turned off. do. In addition, a flicker signal of "+111" is set for display elements that should flicker, and "O" for display elements that are not caused to flicker, and the signals are sent to the old data input terminals of register 5 as DTO to DT6 for each row. Further, a signal specifying the write address of each flicker signal is input to the write address input terminal of the register 5.

As a result, the display signal and flicker (g) for each display element are set in the control circuit 4 and register 5, respectively.

On the other hand, the control circuit 4 outputs an encoded signal SO~$2 of 3 pins which repeatedly changes from decimal representation rOJ to "7" based on the clock signal CLK output from the oscillator 6, and inputs it to the decoder 2. , a timing signal S that is decoded by the decoder 2 to select the driving vJ line in the row direction of the display circuit 1.
C1 to SC8 are output. Therefore, when the processing circuit 3 sets the display 1 for the 6×8 display elements in this state, the control circuit 4 changes the encode signals SO to S2 by using the display signals as signals OL1 to DL6 for each row. In synchronization with the timing, that is, the display signal of the first row is time-divisionally output at the timing when the decimal display value of the signals SO to $2 indicates "i", and the signals DL1 to DL (i is outputted to the second group). !・Input to circuit 9.

On the other hand, the frequency dividing circuit 7 divides the clock signal CLK to form a flicker period signal FT of a desired period, and the (1-J
The signal FT is input to the first gate circuit 8.

Further, after the flicker signal input/output is set, the register 5 receives the encode signals SO to S2 as read address signals, thereby outputting the flicker signals of each display element in a time-division manner on a row-by-row basis. In other words, encoded signal \”3S
When the decimal display value of O-82 is ``jj'', the display element for the 1st row day is flickered for D11~l-[)i6 J?j
When [i + I J, the flicker signals for the display elements D (i + 1) 1 to LD (i + 1) 6 in the i + I J row are output to the hour and minute switch 1 [.

The flicker signals FDL1 to FDLf3 for each row are the first
The gate circuit 8 performs an AND with the flicker period signal FT, and the signal FT is input to the second circuits 1 to 9 every period.

Then, in the second group 1 circuit 9, the display signal and the flicker signal in the same row and in the same column are ANDed,
The results are input to the column-side drive circuit of the display 1.

Therefore, if the flicker signals output from the first gate circuit 8 are FDL1' to FDL6', DLI
1'=1 DL2 XFDL2'=1 D16
The lines are changed one by one by timing signals SC1 to SC8.
The timing signal SC
1 to 3 of the display elements in the row selected by SC8
Current flows only to the display element whose 1 side is driven to "0",
It will turn on.

Since the timing signals SC1 to SC8 repeatedly change with the period of the clock signal CLK, the display elements LD11 to SC8 in each row
LD16. LD21~LD2f3. ...l[)
81 to LD8G are turned on or off in accordance with a display signal that is selected at a cycle eight times that of the clock signal CLK and input to the column-side drive line. In this case, since the clock signal CLK is a signal with an extremely short cycle of, for example, about 640 μs, each row is driven! Even if the 11J element is selected at eight times the frequency, it appears to Iruma to be always on or always off.

Figure 3 shows the clock signal CLK and timing signals SC1 to
A timing chart of SC8 and the flicker periodic signal FT is shown, and FIG. 'i53 shows an enlarged view of the timing relationship in section A, and FIG. 4 shows an enlarged view of the timing relationship in section B.

In Figure 2, the display (No. 8 DL1 and flicker signal F
DLI shows 1'' at the timing of SCO~5G2=1 (in decimal notation), but the flicker period signal FT is 'O'.
” (no flicker), display element LD1
1 indicates that it is always lit. Also, SCO~
At the timing when 5C2=4, the signal DL1="1",
Signal FDL1 = 110 n is shown and further SCO~
At the timing when 5C2=5, the signal DL1-"1",
The signal FDL1 is “1”, but the signal FT is “○”.
'' indicates that the display elements LD41 and LD51 in the first column of the fourth row and the first column of the fifth row are always lit.

On the other hand, in diagram M4, the signal F T = “1”
Therefore, the display elements LD11 and LD51 at the timing when the signal FDL1 becomes 1" become gate lights even though the display signal DL1="1", and the flicker signal FDL1 does not become "1". Display element LD
This indicates that only 41 is lit.

That is, by controlling the flicker signals FDL1 to FDLθ, a desired display element can be made to blink at the cycle of the flicker cycle signal FT.

Therefore, for example, the flicker period signal FT is set so that the sections ``0'' and 1'' are each 250 m5 as shown in FIG. 2, and the flicker signal FDLI as shown in FIG. When set, display element 1 [
)11 and l[)51 blink at a cycle of 2H2<8×250ms>.

Note that if you want to stop the flickering operation of a flickering display element, use the flicker signal FD for that display element.
Just set L to LL OII. FDL= (L O1
After setting it to 1, the display element is controlled to be turned on or off only by the display signal DL.

[Effect of the Invention 1] As explained above, according to the present invention, the processing circuit only sets the flicker signal for the display element to be flickered in advance in the register, so that after setting the flicker signal is Other processing can be performed without any involvement. Therefore, the burden on the processing circuit! ! Reduce, display]!
l! This has the effect of improving the throughput of other processes.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing one embodiment of the present invention, and FIGS.
The figure is a time chart for explaining the operation of the embodiment. DESCRIPTION OF SYMBOLS 1... Display device, 2... Decoder, 3... Processing circuit, 4... Control circuit, 5... Register, 6... Oscillator, 7... Frequency dividing circuit, 8...・First gate circuit, 9
...Second Goo 1~Circuit, l[)11~LDIQ,L
D81 to LD8G...Display element. Figure 1

Claims (1)

[Claims] A display device in which m×n display elements are connected in a matrix of m columns and n rows, a decoder that outputs a timing signal instructing the display timing of each row, and m×n display elements. a processing circuit that sets a display signal for turning on or off;
a control circuit that inputs an encoded signal representing the display timing of each row to the decoder, and supplies a display signal set from the processing circuit to the display device row by row in synchronization with the display timing of each row; In a display device that controls turning on or off of m×n display elements simultaneously and on a row-by-row basis in a time-division manner, a flicker signal is sent from the processing circuit to any display element among the m×n display elements. A register that stores the flicker signal in units of rows and outputs the flicker signals in units of rows according to the encode signal output from the control circuit; a second gate circuit that outputs an AND signal of an output signal of the first gate circuit and a display signal output from the control circuit as a display signal to the display device; 1. A display device comprising: a display device comprising: a display element having a flicker signal set by the processing circuit blinking at a desired flicker cycle;