JPS6376352A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form element isolation bands on which insulating materials are buried into the U grooves so as to obtain IC, a high quality by sticking a silicon oxide film on the whole surface including the inside of the U grooves by a vapor growth method in which organic silicon and oxygen are used as source gas and carrier gas, respectively. CONSTITUTION:While a silicon substrate 11 is heated at 600 deg.C to 700 deg.C, oxygen as carrier gas is made to flow into a reactive liquid container 12 and organic silicon liquid 20 held in the container 12 is bubbled and the organic silicon is carried into the reaction chamber 10. While vacuum exhaustion is performed by means of an exhaustion port 15 so that pressure inside the reaction chamber 10 is reduced, the organic silicon is thermally decomposed on a surface of the silicon substrate 11 and made to react to oxygen so that a SiO2 film is sticked thereon. Since the SiO2 film 16 growing in this way by the reduced-pressure CVD method, in which organic silicon is used as decomposition gas, is excellent in its coverage, the SiO2 film is almost fully buried into the U grooves. Therefore, bad effects of crystal defects induced by an IOP method can be removed and so IC, a high quality can be obtained.

Description

[Detailed Description of the Invention] [Summary] This is a method for forming an element isolation band by U1 separation, in which silicon oxide is grown on the entire surface including the inside of the U groove by a vapor phase growth method using organic silicon as a source and oxygen as a carrier gas. is applied and heat treated.

In this way, an element isolation band is formed in which the U-groove is filled with an insulator, which helps improve the quality of the semiconductor device.

[Industrial Field of Application] The present invention relates to a method for manufacturing semiconductor devices such as ICs, and more particularly to a trench isolation method for isolating semiconductor elements.

In the manufacturing method of semiconductor devices, methods of forming semiconductor devices to further improve the quality thereof are constantly being studied, and the present invention is an improvement proposal regarding the trench isolation process.

[Prior Art] Now, in an IC, a large number of semiconductor elements (cells) are provided on a semiconductor substrate, and element isolation bands are formed to electrically isolate these semiconductor elements. Moreover, although various methods have been proposed for such device isolation bands,
To date, a particularly prominent element isolation method is the trench isolation method applied to bipolar ICs, also known as l0P (Isolation with Oxide).
This is also called the polysilicon method.

This is a method of burying a polycrystalline semiconductor film in a trench via a silicon oxide film (Si02 film) and covering it with a silicon oxide film. Initially, the crystal orientation of the substrate is used to
This was a so-called method for forming a groove separation zone in which a V-shaped groove was formed by wet etching. However, in recent years, with the development of the dry etching method and the demand for higher integration, a method of forming a so-called U:a separation zone in which a U-shaped groove is formed by dry etching has become widely used. It is because the U-shaped groove is V
This is because it is more suitable for miniaturization than 'a.

FIGS. 3(a) to 3(dl) show cross-sectional views in the order of steps of a method for forming a U-groove separation band by the conventional IOP method. First, as shown in FIG. 3(a), a film is formed on a silicon substrate 1. Thickness 1000
A silicon nitride film (Si3N4 film) 3 having a thickness of 2000 mm is formed through the SiO□ film 2, and only the silicon substrate 1 in the U-groove formation region is exposed. Here, SiO2 film 2
is a buffer layer to avoid stress on the substrate, and is directly
This is because when a 3N4 film is deposited on a silicon substrate, stress is generated and the substrate is damaged.

Next, as shown in FIG. 3(b), a etchant with a width of 1 μm and a depth of 3 to 5 μm is etched using a reactive ion etching (RIE) method using chlorine-based gas. Form II4.

Next, as shown in FIG. 3 (C1), after removing the Si3N4 film 3, a heat treatment is performed at a high temperature of about 1000° C. to form a 5i02 film (thickness: 3000 mm) 5 inside the groove 4, and further, A thick polycrystalline silicon film 6 is deposited on the surface including the inside of the trench by low pressure vapor deposition (low pressure CVD), and the inside of the trench 4 is buried.

Next, as shown in FIG. 3(d), the polycrystalline silicon film 6 on the surface is etched or polished to the 5i02 film 5 to make it flat, and the polycrystalline silicon film on the groove surface is further thermally oxidized to form the 5i02 film. 7, thus completing the device isolation band of groove isolation.

[Problems to be Solved by the Invention] However, in the method of forming a U-groove separation band using the IOP method, the polycrystalline silicon film on the groove surface is thermally oxidized to generate the Si○2 film 7 (camping oxidation). It has been found that the formation of the 5i02 film causes the volume to expand, which puts stress around the groove and induces crystal defects.

This is thought to be due to the fact that as ICs have become smaller, the effect on device characteristics has gradually become more noticeable. Furthermore, when a high concentration p shadow region of a pnp transistor is provided close to the U groove, crystal defects in that region increase significantly. This increase in crystal defects has an adverse effect of deteriorating device characteristics, such as increasing leakage current.

Therefore, it is desirable to bury something other than the polycrystalline silicon film 6, for example, a 5i02 film, inside the U groove.
When insulators such as 5i02 film or PSG film (phosphorus silicate film) are deposited by conventional low pressure CVD method, the coverage of these insulator films is insufficient and the U.
The inside of the groove cannot be buried sufficiently, creating a cavity. Moreover, due to the miniaturization of ICs, the aspect ratio (horizontal to vertical ratio) has increased, and the depth is now 4 μm for a groove width of 1 μm.
Since the thickness is about 1 μm, conventional low pressure CVD method,
For example, in the method of oxidizing and depositing monosilane gas,
It is impossible to bury the 5i02-based film in the U-groove.

The present invention solves these problems and proposes a method of forming an element isolation band by U-groove isolation in which an insulator is buried inside the U-groove.

[Means for solving the problem] The purpose is to form a U-groove in a semiconductor substrate, and to grow the entire surface including the inside of the U-groove using a vapor phase growth method using organic silicon as a source and oxygen as a carrier gas. This is accomplished by a method of manufacturing a semiconductor device that includes the steps of depositing silicon oxide and then heat-treating.

[Function] That is, in the present invention, the inside of the U-groove is grown to 5i by a vapor phase growth method using organic silicon as a source and oxygen as a carrier gas.
02 film and then heat-treated.

Then, an element isolation zone is formed in which the 5i02 film is buried in the U-groove, and the element isolation zone made of such a U-groove does not give stress to the surrounding area.

[Example code] Hereinafter, embodiments will be described in detail with reference to the drawings.

FIGS. 1(a) to (dl) show cross-sectional views in the order of steps of a method for forming a U-groove isolation according to the present invention. First, as shown in FIG. 1(a), a 5i02 film 2 is (thickness 1000), 5iHIN4 film 3 (thickness 200)
0), and the silicon substrate 1 is exposed only in the U-groove formation region. Next, as shown in the same figure (b), a width of 1 μm and a depth of 3 to 5 μm was formed using RIE method using chlorine gas.
A groove 4 is formed by etching.

Next, as shown in FIG. 1(C), S
After removing the i3N4 film 3 by etching,
A 5i02 film (thickness: 3000 mm) 5 is formed inside the groove 4 by heat treatment at a high temperature of 0°C, and then a thick 5i02 film 16 with a thickness of 1 to 2 μm is formed on the surface including the inside of the groove by low pressure CVD. to bury the inside of the groove 4. This SiO
□The membrane 16 grows laterally from the sides of the groove inside the groove 4, so it is buried with a joint surface or a slight cavity formed in the bone at the center of the groove.

Figure 2 shows a CVD method for performing the low pressure CVD method according to the present invention.
A schematic diagram of the apparatus is shown, and 10 is a reaction chamber.

11 is a silicon substrate, 12.13 is a reaction liquid container, 14
1 is an oxygen gas inlet, and 15 is an exhaust port. Using such a device, the silicon substrate 11 is heated to 600 to 700°C, while oxygen gas is used as a carrier gas to flow into the reaction liquid container 12 to bubble the organic silicon liquid 20 held in the container 12. Then, organic silicon is carried into the reaction chamber 10, and the pressure inside the reaction chamber 10 is reduced to about I Torr while being evacuated from the exhaust port 15, and the silicon substrate 11 is
Organic silicon is thermally decomposed on the surface and reacted with oxygen (02) to form a St○2 film 16. Organic silicones include, for example, tetraethyl orthosilicate (Tetra t
! T
EOS; (C2H50) 4 Si) is used.

The 5i02 film 16 grown by the low-pressure CVD method using organic silicon as a decomposed gas has extremely good coverage, so the 5i02 film 16 is almost fully grown in the U-groove.
buried in

Furthermore, in the low pressure CVD method using the CVD apparatus shown in FIG.
Bubble the organic phosphoric acid solution 30 held in the reaction chamber 1.
You may carry phosphoric acid into 0 at the same time.

At that time, a PSG film grows, but at that time, triethyl phosphate (Tri Ethyl phosphate) is added to this organic phosphoric acid.
Phosphate) etc. are used.

Thereafter, as shown in FIG. 1(d), after heat treatment is performed at 900 DEG C. for 30 minutes in a dry nitrogen gas atmosphere, the 5i02 film 16 on the surface is polished or etched to the 5i02 film 2 to be flattened. This heat treatment is a buried 5i02
This is to stabilize the membrane 16 and allow the bonding surface to disappear. In addition, when PSG film is made by containing phosphorus,
Since it can be melted by heat treatment, it is particularly effective for filling U-grooves. Further, chemical polishing using acidic ammonium fluoride is suitable for polishing, and full-surface RIE using a fluorine-based reactive gas is suitable for etching.

Now, if the above formation method is used, compared to the conventional IOP method explained in FIG. 3, there is no need for capping oxidation, so crystal defects will not occur around the U groove, and
The inside of the U groove can be sufficiently filled with the 5i02 film. Therefore, the adverse effects of crystal defect induction caused by the IOP method are eliminated, and the quality of the IC is improved.

[Effects of the Invention] As is clear from the above description of the embodiments, according to the present invention, the quality of highly integrated ICs can be greatly improved.

[Brief explanation of the drawing]

FIGS. 1(a) to (d) are cross-sectional views in the order of steps of the groove isolation forming method according to the present invention. FIG. 2 is a low pressure CVD W installation related to the present invention. 1A and 1B are step-by-step cross-sectional views of a conventional trench separation forming method. In the figure, 1 is a silicon substrate, 2 and 5 are 5i02 films, and 3 is a Si
3N4 film, 4 is a U-groove, 6 is a polycrystalline silicon film, 16 is a grown 5i02 film, 20 is organic silicon': I7 (TE01), and 30 is organic phosphoric acid. In fact, there are 19 types of 5 lobe shapes.
1 Figure 'tree f) shape &634 no, Q -2E2-norL
/+lJ tp'ribFigure 3

Claims (1)

[Claims] A method for forming a U-groove element separation band in a semiconductor device, which method involves forming a U-groove in a semiconductor substrate and using a vapor phase growth method using organic silicon as a source and oxygen as a carrier gas on the entire surface including the inside of the U-groove. A method for manufacturing a semiconductor device, comprising the steps of depositing silicon oxide and then heat-treating.