JPS6378639A - Serial data transmitter/receiver - Google Patents

Abstract

PURPOSE:To obtain a communication equipment by which a high level of processing can be performed comparatively easily, with simple constitution, by constituting a device with a means to increase or decrease the output of a counter to which a transmission/reception clock is supplied, a control means to generate the active state of the above means, and a memory means. CONSTITUTION:The main part of the titled device is constituted of a down- counter (or an up-counter) 100 of four bits to which the transmission/reception clock is supplied through a serial clock terminal 10, an incrementor (or a decrementor) 150 to which the output of the down-counter (or the up-counter) 100 is supplied, and which increases (or decreases) the count data of the counter, an NAND gate 1 which sets the incrementor (or the decrementor) 150 in the active state time of transmission or reception, and a random access memory 300 in which a parallel data is transferred between a data bus 200, and the data of a bit position decoded by the output of the incrementor (or the decrementor) 150 is transferred between a serial input/output terminal 20.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a serial data communication device, and provides a transmitting/receiving device that has a simple configuration and can handle advanced communications, and is particularly suitable for microprocessors. This is what realizes the device.

BACKGROUND OF THE INVENTION Serial data communication devices, which have been widely used in one-chip microprocessors, are composed of shift registers, shift counters, and buffer registers.
This is disclosed in Publication No. 82 (hereinafter abbreviated as Document 1).

Problems to be Solved by the Invention Incidentally, since the device shown in Document 1 is mainly composed of random logic circuits, the number of wires between each circuit block is large, and the circuit configuration becomes complicated. (When communicating a large amount of data at once, much of the processing must be done by software, and the circuit configuration must be changed each time to perform more advanced communication or high-speed data transfer.) There was a need.

Means for Solving the Problems In order to solve the above-mentioned problems, the serial data transmitting/receiving device of the present invention includes a counter to which a transmitting/receiving clock is supplied, and an output from the counter that is incremented or decremented. parallel data is exchanged between an incrementing means or decrementing means, a control means for activating the incrementing means or the decrementing means either during transmission or reception, and a data bus;
The apparatus includes a communication means comprising a memory, through which data at a bit position decoded by the output of the increment means or the decrement means is exchanged with a serial input/output terminal.

Function The present invention has a simpler structure due to the above-described structure, and
Moreover, it is possible to realize a communication device with great versatility.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 shows a configuration diagram when a serial data transmitting/receiving device according to an embodiment of the present invention is applied to a microprocessor. Parallel data is transmitted between a counter 100, an incrementer 150 to which the output of the down counter 100 is supplied and increments the count data, a NAND gate 1 which activates the increment 150 upon reception, and a data bus 200. The main part is constituted by a random access memory 300 to which data at a bit position decoded by the output of the incrementer 150 is transferred to and received from the serial input/output terminal 20. Further, the output of the down counter 100 is AN
is supplied to the D terminal of the D flip-flop 4 via the D gate 2 and the OR gate 3;
The output signal of is supplied to the transmission/reception operation completion notification terminal 30, and the
The interrupt request signal is configured to serve as an interrupt request signal to the microprocessor via the microprocessor. Furthermore, reset terminal 4
0. The clear terminal 50 is connected to a non-latch type output port of the microprocessor and is supplied with a reset signal by software, and the interrupt disable pin 60 and the frame length selection terminal 70 for transmitting/receiving data are both connected to the latch type output port of the microprocessor. These are used for software interrupt control and interrupt timing switching. Further, the signal supplied to the serial input/output terminal 20 is applied to the serial data output terminal 310 of the random access memory 300 via the Schmitt type inverter 6 and the inverter 7, and the signal is applied to the serial data output terminal 310 of the random access memory 300. 320 is connected to the D@ terminal of the D flip-flop 8 for waveform shaping.
The output signal is sent to the serial input/output terminal 20 via the 3-state inverter 9. On the other hand, a timing signal generated by a timing signal generation circuit 500 from a clock signal supplied to the serial clock terminal 10 and a clock signal supplied to the system clock input terminal 90 is input as a serial data read clock input to the random access memory 300. It is supplied to terminal 330.

In addition, the control terminal of the 3-state inverter 9 and N
A transmission/reception switching terminal 80 to which the input terminal of the AND gate 1 is connected is connected to a latch-type output port of the microprocessor and used for switching transmission/reception by software, and a control signal based on a microinstruction is supplied to the parallel data load terminal 81. A select signal for activating the parallel input/output section of the random access memory 300 is supplied to the block select terminal 82.

The operation of the transmitting/receiving device configured as described above will be explained based on the configuration diagram in FIG. 1 and the timing chart of the main parts shown in FIG. 2.

First, FIG. 2A shows the clock signal waveform supplied to the serial clock terminal 10, FIG. 2B shows the reset signal waveform supplied to the reset terminal 40, and FIG. C,D.

E and F both show the output signal waveforms of each focus of the down counter 100, and are shown in FIG. 2G.

H are NAND gates 1 and 1, respectively. 2 shows the output signal waveform of the AND gate 2, FIG. 2 shows the output signal waveform of the D flip-flop 4, and FIG.
2 shows how the serial data sent to the serial input/output terminal 20 changes, and FIG. 2 shows the timing at which the data supplied to the serial input/output terminal 20 is read into the random access memory 300. It's ours.

In order to transmit serial data using the device shown in FIG. 1, as shown in FIG. 200
16-bit or 8-bit transmission data is written to the random access memory 3+110. continue,
If the level of the transmission/reception switching terminal 80 is shifted to the transmission state "l" and a clock signal for transmission is supplied to the serial clock terminal IO, the count value of the down counter 100 changes as shown in FIG. 2 every time the leading edge arrives. C
-F, as shown in [1110F.

[1101], . . . , and accordingly, the bit position of the data of the random access memory 300 sent to the D terminal of the D flip-flop 8 is also switched. As a result, the D flip-flop 8
Transmission data is sent to the serial input/output terminal 20 every time the leading edge of the clock signal supplied to the clock signal arrives, but the count value of the down counter 100 is [
1111], the output level of AND gate 2 becomes 1.
2, the output level of the D flip-flop 4 shifts to 1° at the trailing edge of the clock signal supplied to the serial clock terminal 10, as shown in FIG. A signal is sent out. As a result, the microprocessor starts an interrupt processing routine, rewrites 16-bit or 8-bit transmission data from data bus 200 to random access memory 300 as necessary, and prepares for subsequent data transmission.

As can be seen from FIGS. 1 and 2, when the level of the frame length selection terminal 70 is "1", the output of the D flip-flop 4 becomes "1" after transmitting 16 bits of data. However, when the level is 0°, the output of the D flip-flop 4 shifts to "1°" when 8 bits of data have been transmitted.

Incidentally, an output signal from a timing signal generation circuit 500 is supplied to one input terminal of the NAND gate 1 and the serial data reading clock input terminal 330 of the random access memory 300 in FIG. The operation of 500 will be explained based on the timing chart shown in FIG.

FIG. 3A shows a clock signal supplied to the system clock input terminal 90, and FIG. 3B shows a clock signal for transmission and reception applied to the serial clock terminal 10. Figures C, D, and E show the output signal waveforms of the D flip-flops 501, 502, and 503, respectively, and Figure 3F shows the serial data reading clock input terminal 330 via the NOR gate (504).
This figure shows the output signal waveform sent out. In addition,
When the level of the transmission/reception switching terminal 80 is at "1" in the transmission state, the signal waveform in FIG. 1G and the signal waveform in FIG. 3E are the same.

Now, the level of the transmission/reception switching terminal 80 in FIG.
°, the output level of the NAND gate 1 depends on the output of the D flip-flop 503 constituting the timing signal generation circuit 500, and as shown in FIG. It shifts to "1" after the leading edge of the clock signal arrives, and returns to "0" after the trailing edge arrives. On the other hand, when the output level of the NAND gate 1 shifts to "1", the incrementer 150 becomes active and sends data that is 1 larger than the count value of the down counter 100 at that time to the random access memory 300. , the serial data read clock input terminal 330 has the N
While the output level of the AND gate 1 is shifting to 1°, a read clock signal as shown in FIG. 3F is supplied. Therefore, in the device shown in FIG. 1°, that is, in the serial data transmission mode, the random access memory 30 immediately after the leading edge of the clock signal applied to the serial clock terminal 10 arrives.
After the data previously stored in 0 is transmitted, the down counter 100 counts down to prepare for selecting the next bit data in the random access memory 300, but immediately after the trailing edge of the same clock signal arrives. The immediately preceding bit position is selected by the incrementer 150, and then the timing signal generation circuit 5
Serial data reading clock input terminal 33 from 00
0 will be supplied with a read clock signal. As a result, after data is transmitted to each bit position of the random access memory 300, the serial clock terminal 10 is
The data on the serial input/output terminal 20 is read at the trailing edge of the transmission clock applied to the serial input/output terminal 20.

This type of transmit data echo back function can not only be used to check whether there is a conflict in transmit operations when many transmit/receive blocks are connected to the same serial data line, but also can be used to check any number of bits in one frame. Complex communications such as allocating one part for sending and the other for receiving can be easily performed.

In this way, the timing signal generation circuit 500 is used to set the timing for reading serial data from the serial input/output terminal 20 into the random access memory 300.

Note that in order to receive normal serial data, the state of the down counter 100 is set to [1] in the same way as when transmitting data.
1111, reset the D-flip block 4, and shift the level of the transmission/reception switching terminal 80 to the receiving state of "0", the incrementer 150 will always be in the active state, and the serial clock terminal 10 will be in the active state.
When a reception clock signal is supplied to the down counter 100, the count value of the down counter 100 changes each time the leading edge arrives, and accordingly, the data written from the serial input/output terminal 20 to the random access memory 300 changes. The bit position is also switched, and the count value of the down counter 100 is written to the focus position selected when the read clock is supplied from the timing signal generation circuit 500 to the serial data read clock input terminal 330. is [111
1], an interrupt request signal is sent to the interrupt output terminal 31 at the trailing edge of the clock signal supplied to the serial clock terminal 10, as in the case of transmission. As a result, the microprocessor starts an interrupt handling routine, which causes data bus 2 to be transferred from random access memory 300 to data bus 2.
You can read parallel data via 00.

In this way, the serial data transmitting/receiving device shown in FIG. 1 can transmit and receive serial data in the same way as the conventional device. In contrast, the serial data transmitting/receiving device of the present invention can transmit and receive serial data of 16 or 8 bits per frame using only a 4-bit down counter 100 and an incrementer 150. can do. In addition, in conventional devices, the contents of the shift register change when the first leading edge of the serial clock arrives during transmission, so when setting the transmission data to the shift register, the data itself is shifted by one bit. However, in the serial data transmitting/receiving device of the present invention, since switching between transmission and reception is performed by activating or not incrementing the incrementer 150, it is easy to change the bit positions of the transmitted data and received data. I can take action. Accordingly, the circuit configuration is simplified and the proportion occupied by random logic circuits is reduced, making it easier to layout when configuring a one-chip LSI, and suitable for LSI inspection during the production process. Furthermore, since the transmitted and received data is configured to be sent directly from the random access memory 300 at the time of transmission and read directly at the time of reception, without passing through a shift register, it is possible to process a large amount of data at higher speed. That is, in the embodiment shown in FIG. 1, the total number of bits of the random access memory 300 is 1.
Since it is 6 bits, if one frame of data to be transmitted and received has an 8-bit configuration, the random access memory 30
0 has a double buffer function, but
When transmitting and receiving data in which one frame consists of 16 bits, there is no double buffer function, so it is necessary to transmit and receive parallel data to and from the data bus 200 each time one frame is transmitted and received. However, the down counter 10
By increasing the number of bits of 0 and the random access memory 300, a multi-stage buffer configuration can be easily achieved, which allows more information to be handled at once, and advanced communication is also possible.

Incidentally, FIG. 4 is a circuit wiring diagram showing a specific example of the configuration of the random access memory 300, and a unit memory cell is composed of an inverter 301 and a 3-state inverter 302. For example, the serial data in FIG. The level (CK) of the read clock input terminal 330 is “1”
If the level of the AND gate 303 to which the output of the down counter 100 is supplied is also l°, the 3-state inverter 304 becomes active and the data (SDA) of the serial input/output terminal 20 is The data is written into the memory cell via the Sl terminal shown in FIG. Also,
In the transmitting state, if the level of the transmitting/receiving switching terminal 80 is "1", the output side of the 3-state inverter 9 in FIG. 1 is connected to the serial input/output terminal 20, so that at the leading edge of the serial clock signal , the output of the memory cell at the bit position selected by the decoder including the AND gate 303 is sent to the serial input/output terminal 20 via the SO terminal in FIG. State buffer 305 becomes active, and 3-state inverter 306 becomes active when reading parallel data.

Effects of the Invention As is clear from the above description, the serial data transmitting/receiving device of the present invention uses a counter to which a transmitting/receiving clock is supplied (in the embodiment, this counter is constituted by a down counter 100, but of course an up counter ) and incrementing means or decrementing means for incrementing or decrementing the output of the counter (in the embodiment, the incrementing means is provided by an incrementer 150 that increments the count output of the down counter 100). However, if the counter is an up counter, a decrement means for decrementing the count output of the up counter is used instead of the increment means. Alternatively, parallel data is exchanged between a control means (consisting of a NAND gate 1 in the embodiment) that activates the decrement means and a data bus 200, and the output of the increment means or the decrement means A memory means (a random access memory 300 is used in the embodiment, but a latch type memory may also be used) is provided for transmitting and receiving data at a bit position decoded by a serial input/output terminal. By applying the present invention, it is possible to realize a communication device with a simple configuration, and by applying the present invention, it is also possible to obtain a communication device that can perform advanced processing relatively easily. It has a certain effect.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a serial data transmitting/receiving device according to an embodiment of the present invention, FIGS. 2 and 3 are timing charts of the main parts of FIG. 1, and FIG. 4 is a configuration example of a random access memory. FIG. 1... NAND gate, 20... serial input/output terminal, 100... down counter,
150...Incrementer, 200...
・Data bus, 300...Random access memory, 1...NAND gate, 20...
・Serial input/output terminal, 100...Down counter, 150...Incrementer, 200...
...Data bus, 300...Random access memory.

Claims (2)

[Claims] (1) A counter to which a transmission/reception clock is supplied, an incrementing means or decrementing means to which the output of the counter is supplied and incrementing or decrementing the output, and the incrementing means or the decrementing means at the time of transmission or reception. Parallel data is exchanged between a control means for activating the control means and a data bus, and data at a bit position decoded by the output of the increment means or the decrement means is exchanged between a serial input/output terminal. A serial data transmitting and receiving device consisting of memory means. (2) It has a read/write switching terminal and a block select terminal, and when the block select terminal is activated, parallel data is transferred between the data bus and the data bus according to the level applied to the read/write switching terminal. A serial data transmitting/receiving device according to claim 1, characterized in that the serial data transmitting/receiving device is provided with a random access memory that is transmitted and received by a serial data transmitting/receiving device.