JPS6384149A - Manufacture of semiconductor memory - Google Patents

Abstract

PURPOSE:To make the area of a memory small, by making a mask which is used for forming a through hole in a thick insulating film remain on a word line, which is formed by the gate electrode of a first conductor layer, and on a substrate, and utilizing the mask as an interlayer insulating film between a first capacitor electrode using the gate electrode of a second conductor layer and said word line. CONSTITUTION:A P-type layer 2 is epitaxially grown on a P<+> type Si substrate 1. An island shape is formed out of an SiO2 isolating region. The surface is covered with a thin gate insulating film 5. A gate electrode 6, which is to become a word line, is provided thereon. Then, with the electrode as a mask, N<+> type source and drain regions 3 are formed by diffusion. A thick insulating film 7 for forming a deep hole is deposited on the entire surface including the regions 3. The deep hole 8 penetrating into the substrate 1 is formed by anisotropic etching. A thin insulating film 9 is deposited on the bottom and the wall of the hole and the surface. Thereafter a photoresist film 10 is buried in the hole 8. With the films 10 and 7 as masks, the film 9 is etched and the regions 3 are exposed. A second conductor layer 11 and a second thin capacitor insulating film 12 are formed so as to cover the region 3.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor memory manufacturing capabilities, and in particular to a dynamic MO3 random access memory (hereinafter referred to as dynamic MO8RAM) that can be highly integrated. )
The present invention relates to a semiconductor memory manufacturing method suitable for manufacturing a semiconductor memory.

[Conventional technology]

In conventional dynamic MO3RAM, in order to reduce the area of the memory cell, deep holes are formed in the surface area of the semiconductor substrate, and charges are stored inside the holes. A structure has been proposed in which nine product capacitors are formed to obtain a large memory storage capacity. (IEEETransactions on El
ectron Devices) E1D (E
D) -31, number 6, pages 746-753, 19
1984) The memory cell structure shown here has problems such as alpha rays etc. being mixed into the stored charge and memory information is easily lost, and microfabrication is difficult. The invention of Application No. 144754/1983 has been proposed. This structure will be explained using FIGS. 2(a) and 2(b).

Figure 2(a) shows an overview of this dynamic MO3RAM.
118 cross-sectional view, FIG. 2(b) is a plan layout diagram of the semiconductor memory of FIG. 2(a).

In FIG. 2(a), 16 is a P-type silicon substrate.

4 is an element isolation region, and 6 is a gate electrode (word line).

3 is an n-type impurity doped (source, drain) region.

8 is a deep hole formed in the surface area of the silicon substrate 160;
11. is a first thin insulating film formed on the surface of deep hole 8;
13 is a capacitor electrode (gate electrode) formed in the deep hole 8;
12 is a capacitive insulation l formed between capacitive electrodes 11 and 13.
! ! (second thin insulating film). In FIG. 2(b), 15 is a data gland made of metal such as aluminum;
7 is an electrode hole.

That is, in manufacturing this dynamic MO3RAM, the gate electrode 6 serving as the word line is formed using the first conductive layer, and then, after forming the deep hole 8 in the surface area of the silicon substrate 16, a deep hole 8 is formed in the deep hole 8. , insulating film 9, capacitive type ViA 11 formed of the second conductive layer, capacitive insulation! l1
12 and the capacitor electrode 13 formed of the third conductive layer are buried to form a storage capacitor. That is, in this memory cell, the '\f product charge is stored not in the silicon substrate 16 but in the capacitor electrode 11 made of polycrystalline silicon.

However, the description regarding the manufacturing method for realizing this memory cell structure is not sufficiently disclosed.

In particular, the steps before and after forming the deep hole 8 are unclear, and there are several problems in realizing the above structure.

[Problem that the invention seeks to solve]

Hereinafter, the problems of the conventional semiconductor memory structure shown in FIGS. 2(a) and 2(b) and its manufacturing method will be explained.

First, a deep hole 8 is arranged in the silicon substrate 16 between the word lines formed by the gate electrode 6 of the first conductive layer (see FIG. 2(b)). 4? l
! Layer capacitance 'l''! Since a region where the electrode 11 and the n-type impurity doped region 3 of the silicon substrate 16 are directly connected is formed in the upper part of the deep hole 8, the distance between the word lines 6 is widened, and the memory cell Further, in order to connect the capacitor electrode 11 and the n-type impurity doped region 3, it was not possible to easily perform the process of exposing the surface of the silicon substrate 16. Due to the problem, in order to reduce the element dimensions of semiconductor devices such as memory cells, it is necessary to accurately form microscopic deep holes with a diameter of at least one particle or less. The material that serves as the etching mask for forming the semiconductor substrate, that is, has a sufficiently high etching selectivity with respect to the semiconductor substrate, and can be formed and removed uniformly and easily. A mask material that does not damage the substrate, the gate electrode, the word line, etc. has not been obtained.

(■ From ■ above, the dry etching mask for forming the deep hole 8 is a thick film with a multilayer structure using two or more types of materials, and the manufacturing process for the deep hole 8 involves the formation and removal steps of the multilayer film. It was complicated, lacked uniformity, and had low reliability.

The problem (2) will be explained in more detail using FIGS. 3(a) and (b). Figures 3(a) and (b) are similar to Figure 2(a),
FIG. 3B is a schematic cross-sectional view for explaining a method of manufacturing the semiconductor memory shown in FIG.

Conventionally, in order to form deep holes in the surface region of a semiconductor substrate, it is necessary to form an etching mask on the substrate, and then remove the etching mask after etching the deep holes. As shown in a), a multilayered etching mask is used.

In FIG. 3(a), 16 is a p-type silicon substrate, 4 is an element isolation region, 5 is a gate insulating film, 6 is a gate electrode, 3
8 is a deep hole formed in the silicon substrate 16, 7 is an insulating film made of a silicon oxide film, etc.;
A silicon nitride film 4 is formed under the insulating film 7 to protect the element isolation region 4 made of a silicon oxide film from being etched when the insulating film 7 is etched away. That is, the etching mask for forming the deep hole 8 in the silicon substrate 16 has a two-layer structure of the insulating film 7 made of a silicon oxide film and the silicon nitride film 24.

That is, the deep hole 8 is insulated 1i7 and the silicon nitride film 2
To remove the two-layer structure etching mask after forming the two-layer film 4 by etching as a mask, first, the insulating film 7 is completely removed by wet etching, and then the silicon nitride film 24 is etched with hot phosphoric acid. Remove using.

However, in this etching mask removal process, when the insulating film 7 and the silicon nitride film 24 are removed, the gate insulating film 5 exposed on the side surface of the deep hole 8 is removed from the deep hole 8. side etching is done from the edge of the As a result of the miniaturization of memory cells as semiconductor memory becomes more highly integrated,
One side etching of the gate insulating film 5, which could be ignored in the past, has become a problem.

That is, the silicon substrate 16 and the deep hole etching mask 7
As a result of considering the selectivity with respect to 24 and 24 and the uniformity of etching, as shown in No. 3 [S (b).

The thickness of the etching mask (silicon nitride film 24) that remains after the etching of the deep hole 8 is completed is about 0.4 mm, and when this silicon nitride film 24 is removed.

The area where the gate insulating film 5 is etched at the same time is 0.6
As shown in FIG. 3(b), the etching region extends under the gate electrode 6 and even into the element isolation region 4, causing a short circuit between the electrodes and poor insulation.

Furthermore, in the conventional method, as is clear from FIG. 2(a), a second conductive layer (second After forming the gate electrode 11, a patterned photoresist film (not shown) is formed in the deep hole 8 in order to pattern the conductive layer U. Next, after patterning the conductive layer 11 by etching using this photoresist film as a mask,
The photoresist film is removed, and then a capacitive insulating film 12 and a third conductive layer (third gate electrode) 13 are formed on the conductive layer 11. Layer [1
Patterning is performed separately from the conductive layer 11. In the conventional method including such a step, even after the photoresist film removal step, the photoresist film serving as an etching mask or the impurities contained in the photoresist film are not completely removed, and the impurities contained in the photoresist film are not completely removed. The electrical characteristics of the remaining charge storage capacitor (that is, the capacitor electrodes 11 and 13) formed on the deep hole 8 may be deteriorated.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and provide a method for manufacturing a semiconductor memory, particularly a dynamic MO8RAM, which can be highly integrated, requires a small number of steps, and has a high manufacturing yield.

[Means to settle the issue once and for all]

In order to achieve the above object, the semiconductor memory manufacturing method of the present invention is characterized by the following points.

(1) As a dry etching mask for forming deep holes, a thick silicon oxide film or phosphor glass (P
SG: Phospho silicate glass (Phosph)
Dry etching is performed using an insulating film such as an O-3 ilicate glass film, and the insulating film remaining after deep hole etching is used to form a word line consisting of the gate electrode of the first conductive layer and a second layer. It is used for the purpose of insulating and separating the capacitor electrode formed by the gate electrode of the conductive layer.

(2) The insulating film used for insulation separation between the word line and the i-electrode is used as an etching mask for the first thin insulating film formed on the surface of the deep hole.
The upper side of the deep hole (:1
! A region of the semiconductor substrate is exposed and a region (
A direct contact between the substrate and the gate electrode is formed on the upper sidewall of the deep hole.

(3) Furthermore, in one embodiment of the present invention, in order to prevent resist from remaining in the deep hole, the first thin insulating film, the second conductive layer (first capacitive electrode), and the second insulating film are A film (capacitive insulating film) and a third conductive layer (second capacitive electrode) are successively formed on the deep hole, and then these three layers are simultaneously etched by photolithography and etching using a resist mask. Patterning is performed to form a second gate electrode and a third gate electrode.

That is, the present invention includes a first step of forming an insulated gate field effect transistor having a gate electrode formed using a first conductive layer in a predetermined region of a semiconductor substrate; a second step of forming an insulating film patterned for deep hole etching on a semiconductor substrate; a third step of etching the semiconductor substrate using the insulating film as a mask to form a deep hole; At least a fourth step of forming at least one kind of thin insulating film in the deep hole, and a fifth step of forming a second conductive layer at least in the deep hole and on the deep hole etching insulating film. The gist is to include:

In an embodiment of the present invention, in order to realize the feature (3) above, the second conductive layer, the second thin insulating film, and the third conductive layer are provided in the deep hole. After sequentially forming layers and patterning these three layers simultaneously, a fourth conductive layer having a pattern different from the three layers is formed on the third conductive layer.

Furthermore, in another embodiment of the present invention, after forming a shallow hole by etching the semiconductor substrate using the insulating film for deep hole etching as a mask, a thin insulating film is formed on the side wall of the shallow hole; Next, the above-mentioned deep hole etching method M
The deep hole is formed using IIQ as a mask, and then a thin insulating film of a different type from the thin insulating film formed on the side wall of the shallow hole is formed on the sidewall of the deep hole.

Note that the present invention has a structure in which a single capacitive conductive layer is formed in a deep hole formed in a semiconductor substrate via a thin insulating film (see the above-mentioned document 31, number 6
, pp. 746-753, 1984), or a structure in which a conductive layer, a thin insulating film, and another conductive layer are formed within the deep hole via a thin insulating film.

[Effect]

The thick insulating film used as a deep hole etching mask remains on the word line formed by the gate electrode of the first conductive layer and on the semiconductor substrate after the deep hole etching is completed.
This becomes an interlayer insulating film that insulates and isolates the word line from the first capacitor electrode constituted by the gate electrode of the second conductive layer to be formed next.

In addition, since this insulating film has a shape that covers the surface of the semiconductor substrate except for the sidewalls and bottom of the deep hole, the inside of the deep hole is subsequently processed (by etching and removing the first thin insulating film on the upper sidewall of the deep hole). It can be used as an etching mask when forming a direct contact between the substrate and the second gate electrode (first capacitive type JU). In order to connect the gate electrode of the deep hole and the semiconductor substrate at the upper side wall of the deep hole, etching can be easily performed to expose the surface of the semiconductor substrate on a part of the inner surface of the deep hole.

Furthermore, in one embodiment of the present invention, in the step of successively forming the first thin insulating film, the second conductive layer, the second insulating film, and the third conductive layer in the deep hole, 2nd conductive layer and 3rd conductive layer
By forming the conductive layer so that the total thickness of the first conductive layer is more than half of the thickness of the deep hole, the deep hole is
It is completely buried by the thin insulating film, the second conductive layer, the second insulating film, and the third conductive layer. Therefore, in the process of using photoresist to pattern these three layers, the photoresist film does not enter deep holes, so that the photoresist film can be easily and completely removed. This eliminates the characteristic deterioration of the charge storage capacity caused by the photoresist remaining in the deep hole. Note that in order to increase the charge storage capacity, it is preferable to form the second conductive layer thinly and the first conductive quasi-layer thickly.

〔Example〕

Embodiment 1 FIGS. 1(a) to 1(d) are cross-sectional views showing a method for manufacturing an n-channel semiconductor memory (dynamic MOSRAM) according to a first embodiment of the present invention in order of steps. This embodiment is an example of implementing (1) and (2) described in the section of means for solving problems.

First, as shown in FIG. 1(, ), an element isolation region 4 made of a silicon oxide film is placed on a p-type silicon substrate on which a p-type silicon epitaxial layer 2 is grown on a highly doped p-type silicon layer 1. After forming a thin gate insulating film (silicon oxide film) 5 on the p-type silicon substrate, a gate electrode (word W) 6 made of a first conductive layer is formed thereon. By introducing impurities using the electrode 6 as a mask, an n-type impurity doped (source, drain) region 3 is formed in a self-aligned manner to form an insulated gate field effect transistor. Next, a thick insulating film 7 made of a silicon oxide film, a PSG film, etc. is deposited by the CVD method and has a thickness necessary as an etching mask for forming deep holes in the silicon substrate, and then photolithography and dry etching are performed. The insulating film 7 is patterned for deep hole etching by a method to form a mask for forming deep holes.

Next, as shown in FIG. 1(b), anisotropic dry etching is performed using the insulating film 7 as an etching mask.
A deep hole 8 is formed in the mold silicon substrate. Subsequently, a first thin insulating film 9 made of SiO, Si, N4 film, etc. is formed on the surface of the substrate including the surface of the deep hole 8. Furthermore, in the next step, the photoresist film 10 is deposited in the deep hole 8 to a predetermined depth, so that a direct contact portion between the second conductive layer 11 and the n-type impurity doped region 3 is formed as shown in FIG. 1(c). Then, it is buried up to the side wall of the deep hole 8 between the upper end of the deep hole 8 and the upper surface of the photoresist film 10.

Next, the insulating film 9 is etched using the photoresist film 10 and the insulating film 7 as a mask to expose the n-type impurity-doped region 3 of the silicon substrate on the upper side wall of the deep hole 8, as shown in FIG. 1(c). let Subsequently, a second conductive layer 11 made of n-type polycrystalline silicon is formed. This results in
The second conductive layer 11 and the n-type impurity doped region 3 are formed in the deep hole 8.
directly connected at the upper side wall of the Next, using the photoresist film formed in the deep hole 8 and on the substrate as a mask,
Pattern the second conductive layer. This second conductive layer 11 becomes a first capacitor electrode (second gate electrode). Next, a second thin insulating film (capacitive insulating film) is placed on top of it.
form 12. Subsequently, a third conductive layer 13, which becomes a second capacitor electrode (third gate electrode), is formed thereon from n-type polycrystalline silicon. Next, two layers, the third conductive layer 13 and the second thin insulating film 12, are patterned simultaneously. As a result, the gate electrode 6 consisting of the first electrosensitive layer and the capacitor electrode 11 are insulated and separated by the insulating film 7 used as an etching mask for the deep hole 8, so that the capacitor part, that is, the capacitor electrode 11 and 13 can be formed even in the upper region of the gate electrode 6 as shown in the figure, and the capacitance can be increased.

Next, as shown in FIG. 1(d), a single PSG film 4 is formed, a contact hole is opened in the film, and an n-type impurity doped layer 3 is formed.
A first layer metal mold 1415 is formed to be connected to the first layer metal mold 1415.

Thereafter, an interlayer insulating film made of SiO2 or organic resin, a second layer metal electrode, and a surface protection film are formed as necessary to complete the memory.

The first feature of this embodiment is that the deep hole 8 is etched using the thick insulating film 7 as an etching mask, and after this etching is completed, the remaining insulating film 7 is used as the gate electrode 6.
It is used as an insulating isolation region between the capacitor electrode 11 and the capacitor electrode 11. Therefore, the step of removing the insulating film 7, which was conventionally performed, becomes unnecessary.

Conventionally, as explained in detail earlier, a step is required to remove the etching mask for forming deep holes, so during this removal, part of the gate insulation is side-etched, resulting in short circuits between electrodes and poor insulation. However, in this embodiment, since the etching mask is not removed, such a problem does not occur. Further, unlike the conventional method, it is not necessary to form a deep hole etching mask in multiple layers, which simplifies the process and improves manufacturing yield.

The second feature of this embodiment is that, as shown in FIG. 1(b), the upper sidewall of the deep hole 8 is etched using the insulating film 7 and, for example, a photoresist film 10 embedded in the deep hole 8 as an etching mask. Only the first thin insulating film 9 is removed to expose the silicon substrate, and as shown in the first Vi(c),
The electrode 11 and the n-type impurity doped region 3 of the silicon substrate are connected at the upper side wall of the deep hole 8. Since the structure does not connect the capacitor electrode 11 and the n-type impurity doped region 3 on the upper surface of the silicon substrate 16 as in the conventional example shown in FIG. 2(a), the etching mask is removed and the first insulating film is removed. There is no reduction in the thickness of the silicon oxide film on the element isolation region 4 or the gate electrode 6 during patterning in step 9, and a highly reliable memory cell can be constructed.

Embodiment 2 A method for manufacturing an n-channel semiconductor memory (dynamic MOARAM) according to a second embodiment of the present invention is shown in FIGS.
The process order is shown in (d).

In this embodiment, a gate electrode, which is a first conductive layer, and an etching mask for forming a deep hole are used. The steps up to the formation of the insulating film are the same as those in the first embodiment, and are shown in FIG.
) The cross-sectional structure is the same as that shown in ).

Subsequently, as shown in FIG. 4(a), the semiconductor substrate 1
6 is dry-etched to a thickness of about 0.2 to 0.3 ρ using the insulating film 7 as a mask to form a shallow hole 8', and then a silicon nitride film is formed to a thickness of about 50 nm to 120 nm to form an anisotropic After etching back the silicon nitride film by dry etching, the side surfaces of the insulating film 7 and the semiconductor substrate 16 are removed.
A silicon nitride film 20 is left on the side wall of the shallow hole 8' formed in the hole 8'.

In this state, the semiconductor substrate 16 is further dry etched to form a deep hole 8 as shown in FIG. 4(b). At the end of etching, the depth of the deep hole 8 and the semiconductor substrate 16 are
The thickness of the insulating film 7 decreases as shown in the figure, depending on the etching selectivity between the etching film 7 and the insulating film 7 serving as a mask. Subsequently, a silicon oxide film 2 is formed on the surface area of the deep hole 8 by thermal oxidation.
1 (first thin insulating film). Thereafter, the silicon nitride film 20 is removed.

Next, as shown in FIG. 4(c), a capacitive portion, that is, a first conductive layer, which is a second conductive layer, is placed inside the deep hole 8 and on the insulating film 7.
capacitive electrode 11, capacitive insulating film (second thin insulating film) 12
, the second capacitor electrode 13, which is the third conductive layer, is successively formed. At this time, the capacitor electrode (gate electrode) 11
and 13, determine the film thickness. Thereafter, by simultaneously patterning the capacitor electrode 11, capacitor insulating film 12, and capacitor electrode 13 by one photolithography method and dry etching method, it is possible to eliminate the step in which the photoresist film enters the deep hole 8. Next, a thick insulating film such as a silicon oxide film is uniformly formed over the entire surface of the semiconductor substrate, and sidewall insulating film 22 is left only at the ends of capacitor electrodes 11 and 13 by anisotropic dry etching. Subsequently, by forming and patterning a polycrystalline silicon film on the capacitor electrode 13, the gate electrode 1 is formed as shown in FIG. 4(d).
Plates 1 to 23 for drawing out the electrode connection parts of No. 3 are formed. Note that when polycrystalline silicon is used as the gate electrode (capacitor electrode) material, conductivity is increased by phosphorus treatment or ion implantation. Finally, as in FIG. 1(d), interelectrode insulating films, metal electrodes, surface protection films, etc. are formed to complete the memory.

The feature of this embodiment is that the first
In addition to the second feature, the third feature is that the process of introducing the photoresist film into the deep hole 8 is eliminated, and therefore, contamination in the deep hole 8 due to the photoresist film or impurities in the photoresist film can be eliminated. It is.

Fourthly, by forming the insulating film 22 in the form of a sidewall of the capacitive electrode 11.13, inter-electrode insulation between the first capacitive electrode 11 and the plate electrode 23 and mitigation of the steep step difference at the end of the electrode can be achieved. It should be done at the same time.

Although the embodiments of the present invention have been described above, it goes without saying that the present invention is not limited to the above embodiments, and that various changes can be made without departing from the spirit of the invention. For example, in the above embodiment, an n-channel type memory cell is taken as an example, but the present invention can also be applied to a p-channel type memory cell.

Further, in the second embodiment shown in FIG. 4, a p-type substrate is used as the substrate, but as the p-type substrate, a low concentration p-type substrate similar to that shown in FIG. It is also possible to form a charge storage capacitor between the first capacitor electrode 1 and the p-type substrate by using an epitaxial substrate on which a p-type epitaxial layer is formed.

〔Effect of the invention〕

As described above, according to the present invention, a memory cell that can be highly integrated can be realized in a small area, and a highly reliable dynamic memory cell can be manufactured with a small number of manufacturing steps and a high manufacturing yield. Therefore, there is an effect that a dynamic memory can be realized at low cost.

[Brief explanation of the drawing]

FIGS. 1(a) to 1(d) show 11L of the semiconductor memory of the present invention.
FIG. 2(a) is a process cross-sectional view of the first embodiment of the first manufacturing method, and FIG. 3(a), (b) is a schematic cross-sectional view for explaining the conventional technology, FIG. 2(b) are the planar layout diagrams of the conventional semiconductor memory shown in FIG. 2(a), and FIGS. 4(a) to 4(a).
(d) is a process sectional view of the second embodiment of the present invention. 1... High concentration p-type silicon substrate 2... P-type silicon epitaxial layer 3... N-type impurity doped region 4... Element isolation region 5... Gate insulating film 6...
...Goo 1-electrode 7 of the first conductive layer...Insulating film 8 for deep hole etching mask...Deep hole 9.
...First insulating film 10...Photoresist film 11...First capacitor electrode 12 of the second conductive layer...
Capacitive insulating film (first insulating film) 13...Second capacitive electrode of third conductive layer 14...Interlayer insulating film 15.
...Metal electrode (data line) 16...P-type silicon substrate 17...Electrode hole 19.20.24...Silicon nitride film 21...Silicon oxide film 22...Side wall insulating film 23 ...Patent attorney representing plate electrode Junnosuke Nakamura 3- (b)

Claims (1)

[Claims] 1. A first step of forming an insulated gate field effect transistor having a gate electrode formed using a first conductive layer in a predetermined region of a semiconductor substrate; a second step of forming an insulating film patterned for deep hole etching on the semiconductor substrate including the semiconductor substrate; a third step of etching the semiconductor substrate using the insulating film as a mask to form a deep hole; a fourth step of forming at least one kind of thin insulating film in at least the deep hole; and a fifth step of forming a second conductive layer at least in the deep hole and on the insulating film for deep hole etching. A method for manufacturing a semiconductor memory, comprising at least the following. 2. After the fourth step, the thin insulating film on the upper side wall of the deep hole is removed to expose the surface of the semiconductor substrate on the upper side wall of the deep hole, and the fifth step The method for manufacturing a semiconductor memory according to claim 1, further comprising the step of forming a second thin insulating film and a third conductive layer on the second conductive layer. . 3. After sequentially forming the second conductive layer, the second thin insulating film, and the third conductive layer in the deep hole, and patterning these three layers simultaneously, form the third conductive layer. 3. The method of manufacturing a semiconductor memory according to claim 2, wherein a fourth conductive layer having a pattern different from that of the three layers is formed on the first conductive layer. 4. First, a shallow hole is formed by etching the semiconductor substrate using the insulating film for deep hole etching as a mask, and then a thin insulating film is formed on the side wall of the shallow hole, and then the insulating film for deep hole etching is formed. Forming the deep hole as a mask,
Next, a thin insulating film of a different type from the thin insulating film formed on the side wall of the shallow hole is formed on the side wall of the deep hole. .