JPH0750772B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] A semiconductor device using a semiconductor substrate on an insulator such as a so-called SOI (silicon on insulator silicon) substrate, in which a capacitor having a large capacitance is formed in a small area. And a first insulating layer disposed on the supporting substrate, and a first insulating layer disposed on the first supporting layer. , A first conductive layer having a thickness of about 1 μm or less, a second insulating layer arranged on the first conductive layer, and a semiconductor substrate arranged on the second insulating layer. .

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and particularly to a semiconductor device using a semiconductor substrate on an insulator such as a so-called SOI (silicon on insulator) substrate and a method for manufacturing the same. Regarding

There is a strong demand for higher integration in semiconductor memory devices and the like.
Three-dimensional structures such as a trench type and a stack type are being adopted in order to manufacture a memory device having a small area and less soft errors. The semiconductor device of the present invention is particularly suitable for forming a separation / merging type memory cell utilizing a groove.

[Prior Art] FIG. 2 shows an isolation / merging type cell called an IVEC cell in a semiconductor memory device according to the prior art. Lattice-shaped trenches (trench) 105 are formed on one surface 103 of the p-type silicon substrate 101 to define a plurality of matrix-shaped island regions 107. An n ⁺ type source region 109 and an n ⁺ type drain region 111 are formed in each island region 107, and a channel region 113 is defined between them. In this specification, for convenience, the current terminal connected to the bit line is referred to as a source, and the current terminal connected to the capacitor is referred to as a drain. An insulated gate structure 115 is formed on the channel region 113. Except for the side wall of the drain region 111, the insulating film 11 is formed on the side wall of the trench 105 surrounding each island region 107.
6 is formed, a polycrystalline silicon film 117 is formed thereon, and is electrically connected to the n ⁺ type drain region 111. An insulating film 118 is further formed on the surface of the remaining groove 105.
Is filled with a polycrystalline silicon cell plate 119 to form a capacitor with the polycrystalline silicon film 117. That is, the polycrystalline silicon film 117 forms an information storage electrode, and the polycrystalline silicon cell plate 119 also serves as one electrode of the capacitor and an isolation region between cells.

A process for manufacturing such a separation / merging type semiconductor memory cell is shown in FIGS. 3 (A) to (G).

First, as shown in FIG. 3A, first, a lattice-shaped groove (trench) 105 is formed from one surface 103 of the p-type Si substrate 101 toward the inside by anisotropic dry etching or the like, and then an oxide film is formed on the surface. Form 102.

After forming the groove 105 and the oxide film 102, a resist film is formed so as to fill the groove 105 and cover the surface 103 as shown in FIG.
Form 104.

The resist film 104 is entirely etched as shown in FIG. 3 (C), and a desired amount is left on the bottom of the groove 105.

Further, as shown in FIG. 3 (D), a resist film 10 is formed on the surface.
6 is applied, and the portion of the drain region where the contact surface is to be formed is exposed and developed. The oxide film 102 on the side surface of the groove 105 is removed by etching using the remaining resist films 104 and 106 as a mask. In this way, only a part of the side surface of the island region 107 is exposed.

After etching, the resist films 104, 106 are also peeled off. After that, a polycrystalline silicon film 117 is formed as shown in FIG. For example, CVD of non-doped polycrystalline silicon film
And n-type impurities such as phosphorus (P) are vapor-phase-diffused. Here, at the contact surface of the drain region exposed in FIG. 3D, the polycrystalline silicon film 117 directly contacts the surface of the silicon substrate 101.

This polycrystalline silicon film 117 is subjected to reactive ion etching (RIE) as shown in FIG. 3 (F). Due to the directional etching, the polycrystalline silicon film 117 on the bottom surface of the groove 105 is removed to separate the polycrystalline silicon film 117 of each memory cell, leaving only the portion on the side surface of the groove 105, and each island region. 107. Remove the polycrystalline silicon film on the upper surface.

The remaining polycrystalline silicon film 117 as shown in FIG.
An insulating layer 118 is formed by thermally oxidizing the surface of, or by depositing a SiO ₂ / Si ₃ N ₄ / SiO ₂ laminated film or the like. Further, conductive polycrystalline silicon 119 is deposited in the space inside the remaining trench (trench) 105 to fill the trench 105.

After that, an insulated gate transistor in which the drain region 111 is connected to the polycrystalline silicon film 117 is formed in each island region 107 to manufacture a semiconductor memory device as shown in FIG.

In this way, the memory cell area is separated by the trench,
In the semiconductor memory device in which the counter electrode having a predetermined potential is arranged in the trench, the capacitor extends vertically in the trench which also serves as the isolation region, and the cell area can be reduced.

[Problems to be Solved by the Invention] In order to increase the capacitance of the capacitor, the groove should be deeper or
High dielectric film (nitride film,
Ta ₂ O ₅ etc.) or the insulating film may be thinned. However, the method using a high-dielectric material such as Ta ₂ O ₅ has not reached the level of practical use in terms of leak characteristics except for the nitride film. Further, the nitride film is not sufficient for future demand. Further, there is a problem in reliability of dielectric breakdown in thinning the insulating film. Therefore, the method usually used is to make the groove deep. However, making the groove deeper causes problems such as deterioration of the groove shape, instability of the groove interface, and deterioration of embedded coverage.

As described above, according to the conventional technique, it is difficult to manufacture a capacitor having a larger capacitance or a smaller area.

An object of the present invention is to provide a semiconductor device having a structure suitable for forming a large capacity capacitor with a small area.

In addition, the island region where a transistor is formed is continuous to the semiconductor substrate as it is, and if a large amount of carriers are generated by alpha ray irradiation, the carriers may flow into the drain region or the like to cause a soft error.

Another object of the present invention is to provide a semiconductor device capable of enhancing resistance to soft errors.

Yet another object of the present invention is to provide a method of manufacturing such a semiconductor device.

[Means for Solving the Problems] FIGS. 1 (A), (B), and (C) are explanatory views of the principle of the present invention, (A) and (B) show a semiconductor device, and (C) shows The manufacturing method of the semiconductor device of (A) is shown roughly.

In FIG. 1 (A), a first insulating layer 7 is arranged on a supporting substrate 1 having a conductive surface layer 11, and a first conductive layer having a thickness of about 1 μm or less is arranged thereon. Then, the second conductive layer 9 is arranged thereon, and the semiconductor substrate 3 is arranged thereon. Semiconductor substrate 3 is "semiconductor on insulator"
And a thin first conductive layer is sandwiched in the insulator.

A semiconductor device as shown in FIG. 1 (B) can be manufactured by utilizing the structure shown in FIG. 1 (A). In FIG. 1 (B), a groove 13 extending from the surface of the semiconductor substrate 3 to the conductive surface layer of the support base 1 is formed to define a plurality of island regions 15 surrounded by the groove. The side surface of the island region 15 is covered with the third insulating layer 17 except for the contact portion, and the second conductive layer 19 is formed thereon. The second conductive layer 19 electrically connects the first horizontally arranged lower conductive layer 5 and the current terminal 22 of the semiconductor element 16 in the island region 15, for example. Since the first conductive layer 5 faces the conductive surface layer 11 to form a capacitance, the capacitor is connected to the semiconductor element 16.
Further, the fourth insulating layer 21 is formed on the second conductive layer 19, and the conductive region 23 is arranged so as to fill the central portion of the remaining groove 13. The conductive region 23 faces the second conductive layer 19 and forms a capacitor. Further, the conductive region 23 is in contact with and electrically connected to the conductive surface layer 11 therebelow. Compared with the conventional technology, the first conductive layer 5 and the surface layer
The capacity of the capacitor connected to the semiconductor element 16 increases by the capacity formed by 11. Further, the semiconductor element and the capacitor are completely separated from the support base 1 by the insulating layer.

If the conductive region 23 is contacted from above, the conductive region 23 does not necessarily have to make contact with the surface layer 11.

FIG. 1 (C) schematically shows an example of a manufacturing method of the configuration of FIG. 1 (A). Arrangement films 27 and 35 are formed on at least one surface of each of the first silicon substrate 25 and the second silicon substrate 33. The conductive film 2 is formed on the oxide film 27 of the first silicon substrate 25.
9. Form the insulating film 31. After that, the insulating film 31 and the oxide film 35 are formed.
And the two silicon substrates are bonded to each other. In this way, a semiconductor device as shown in FIG. 1 (A) can be obtained.

After that, the first or second silicon substrate is polished to a predetermined thickness, and a groove is formed from the surface of the thinned silicon substrate,
A semiconductor device as shown in FIG. 1B can be obtained by forming various components.

[Operation] As shown in FIG. 1 (A), in the semiconductor structure on the insulator, the conductive layers 5 are arranged on the supporting base 1 having the conductive surface layer 11 with the insulating layers 7 and 9 interposed therebetween. By disposing the semiconductor substrate 3 thereon, a capacitor can be built under the semiconductor substrate 3 for making a semiconductor element. Therefore, the substrate area can be effectively used and the degree of integration can be improved. Further, since the semiconductor substrate 3 and the conductive layer 5 are separated by the support base 1 and the insulating layer 7, a semiconductor device having a strong soft error resistance can be constructed.

As shown in FIG. 1 (B), the semiconductor substrate 3 is divided by a groove 13 to define an island region 15, and the first conductive layer 5 buried below is connected to a semiconductor element 16 formed in the island region, The buried first conductive layer 5 and the conductive layer 19 around the island region 15 serve as an information storage electrode of the capacitor, and the conductive surface layer 11 of the supporting base 1 and the conductive region 23 filling the groove serve as the other electrode of the capacitor which also serves as a separation region. Thus, it is possible to realize a semiconductor memory device having a three-dimensional structure, a small occupied area, a high capacity, and a strong resistance to soft errors.

As shown in FIG. 1C, an oxide film 27, a conductive film 29, an insulating film 31 are formed on one of the two silicon substrates 25 and 33, and an oxide film 35 is formed on the other, and the two are bonded together. Easy first
The structure of Figure (A) can be manufactured.

Example First, a semiconductor device having a novel laminated structure will be described. Basically, in a structure in which an insulating layer is formed on two substrates and the insulating layers are bonded to each other to form one SOI structure bonded substrate, the surface of the supporting substrate is made conductive and the insulating layer is formed. It has a conductive layer embedded therein.

FIGS. 4A to 4D show a method of manufacturing the above semiconductor device according to one embodiment of the present invention.

First, as shown in FIG. 4 (A), two substrates 40 and 50 are prepared. One substrate 40 is a substrate for forming a semiconductor element, and needs to be made of a semiconductor. For example, a silicon substrate. The other substrate 50 is a substrate for providing physical support and a conductive surface layer. For example, although it is formed of a semiconductor substrate such as a silicon substrate, it may be a metal substrate or a dielectric substrate having a metal layer on its surface.

Next, as shown in FIG. 4 (B), insulating films 42 and 52 are formed on one surface of each of the substrates 40 and 50. As the material of the insulating film, oxides such as SiO ₂ , Ta ₂ O ₅ and nitrides such as Si ₃ N ₄ can be used. For example, when the substrates 40 and 50 are silicon substrates, the silicon substrates may be wet-thermally oxidized to form an oxide film. An oxide film or the like may be deposited by chemical vapor deposition (CVD) or the like. Since the insulating film 52 on the support substrate 40 serves as an interelectrode insulating film of the capacitor, if the insulating film 52 has sufficient insulation resistance and withstand voltage, a thinner one is more advantageous for obtaining a higher capacitance. For example, a thermal oxide film with a thickness of about 200Å or less. The insulating film on the semiconductor substrate 40 is one of the insulating films for bonding, and after bonding, it becomes an insulating separation film between the semiconductor element region and the conductive film below. It is preferable to be thick to some extent, for example, the total thickness after bonding is about 1μ
It is a silicon oxide film that becomes m.

As shown in FIG. 4C, a conductive film 54 and an insulating film 56 are formed on the insulating film 52 on the supporting substrate 50. The conductive film 54 serves as an electrode plate of the capacitor. For example, phosphorus (P) is used as the surface resistance.
It is a polycrystalline silicon film with a thickness of about 2000Å doped to 60Ω / □. High melting metals such as W and Mo, high melting metals such as W and Mo,
Other conductive materials such as silicide of transition metal such as Ti may be used. The conductive film 54 is deposited by, for example, CVD. Insulation film 56
Can be made of the same material as the insulating films 42 and 52 described above. For example, when the conductive film 54 is a polycrystalline silicon film, it may be a silicon oxide film formed by wet or thermal oxidation of hydrochloric acid. In that case, the polycrystalline silicon film is made thick due to oxidation.

Next, as shown in FIG. 4 (D), the insulating film 42 and the insulating film 56 on the support substrate 50 are faced to each other and bonded to each other on the semiconductor substrate 40. For example, when the insulating films 42 and 56 are SiO ₂ films, heat treatment at a temperature of about 1000 ° C. or higher, for example, about 1100 ° C.
O ₂ can be stuck together. Adhesion is good when static charge is applied and it is adsorbed by Coulomb force and heat treated. The thickness of the insulating films 42 and 56 before being combined is selected so that the combined insulating film 42 ′ has a thickness of, for example, about 1 μm. afterwards,
The semiconductor substrate 40 is polished to a predetermined thickness, for example, about 4.5 μm
And The total thickness including the support substrate 50 is set to a value suitable for handling, for example, 600 to 650 μm.

If the thickness of the insulating film 54 sandwiched in the insulating film is too large, it is not preferable in terms of processing accuracy. It is preferable to be thin as long as the conductivity can be secured to some extent. Therefore, the thickness is set to 1 μm or less.

5 (A) to (D) are the same manufacturing steps as FIGS. 4 (A) to (D), and FIGS. 5 (A) and (B) are FIGS. 4 (A) and 4 (B). But the intermediate conductive film and insulating film are formed on the semiconductor substrate.

That is, in FIG. 5C, the conductive film 54, the conductive film 44 corresponding to the insulating film 56, and the insulating film 46 of FIG. 4C are formed on the insulating film 42 on the semiconductor substrate 40 forming a semiconductor element. Has been formed.

Therefore, in FIG. 5 (D), the insulating film 46 on the semiconductor substrate 40 and the insulating film 52 on the supporting substrate 50 are brought into contact with each other and bonded to form an integrated insulating film 52 '.

Other points are the same as those in FIGS. 4 (A) to 4 (D).

FIGS. 4 (A) to (D) and FIGS. 5 (A) to (D) show a structure in which one conductive layer is sandwiched in the insulator, but the sandwiched conductive layer is 2 It may be more than one layer.

FIG. 6 shows an example of a manufacturing method of a structure in which two conductive layers are sandwiched.

A semiconductor substrate 40 and a supporting substrate 50 are prepared as shown in FIG. 6A, and insulating films 42 and 52 of, for example, thermally oxidized silicon are formed on the respective surfaces as shown in FIG. 6B. The steps up to this point are the same as those in FIGS. 4 (A) and 4 (B).

Next, as shown in FIG. 6C, an insulating film on the supporting substrate 50
On top of 52, the first conductive film 54, the inter-membrane insulating film 56, the second conductive layer 5
8. An insulating film 59 for bonding is formed. The first conductive film 54,
The second conductive layer 58 can be formed of a conductor such as polycrystalline silicon metal or silicide. Since the second conductive film 58 will be the information storage electrode of the capacitor and will be patterned,
It is necessary to have a predetermined conductivity with a thickness of μm or less. The first conductive film 54 serves as a counter electrode of the capacitor in place of the conductive surface layer of the supporting substrate in the case of FIGS. 4A to 4D and has an arbitrary thickness as long as it has a predetermined conductivity. Good. It is preferable that the inter-film insulating film 56 that serves as the inter-electrode insulating film of the capacitor is as thin as possible and has a dielectric constant as high as possible in order to realize high capacitance. For example, SiO with a thickness of 200Å or less
Formed with _two films.

After that, as shown in FIG. 6D, the insulating film 42 on the semiconductor substrate 40 and the bonding insulating film 59 on the supporting substrate 50 are combined and bonded by heat treatment at about 1100 ° C., for example.

It can be considered that the structure of FIG. 6D includes another conductive film between the conductive film of the structure of FIG. 4D and the supporting substrate. At this time, the conductive surface layer of the supporting substrate is not always necessary. It can also be considered that the conductive surface layer of the supporting substrate is composed of an independent conductive film.

7A to 7D show an example in which a stacked layer of a conductive film and an insulating film is formed on the semiconductor substrate 40 side. Other points are the same as those in FIGS. 6 (A) to 6 (D).

Next, FIGS. 8 (A) to 8 (F) show steps of manufacturing a semiconductor memory device by using the structure made by the manufacturing steps shown in FIGS. 4 (A) to 4 (D).

As shown in FIG. 8A, a semiconductor support substrate 61 made of silicon or the like, a first insulating layer 67 made of SiO ₂ or the like, a first conductive layer made of polycrystalline Si or the like.
65, a second insulating layer 69 such as SiO _{2 and} a semiconductor substrate 63 such as silicon
And a oxide film 64 is formed on the semiconductor substrate 63.
To form. For example, a silicon oxide film or a phosphosilicate glass (PSG) film is deposited by CVD. Apply a resist on it, expose a groove pattern with a width of about 1 μm,
The lower oxide film 64 is patterned, and the semiconductor substrate 63 and the second insulating layer 69 are vertically etched by reactive ion etching using the oxide film 64 as a mask. As an etchant, for example, Si ₂ chlorine etchant to the substrate, fluorine for SiO ₂ (CF ₄ + CHF ₃ or CF ₄ +
H ₂ etc.) An etchant may be used. For polycrystalline Si, plasma isotropic etching of CF ₄ + H ₂ is performed. Thus, the groove 73 as shown in FIG. 8 (A) is dug. The grooves 73 run in a grid pattern on the surface of the semiconductor substrate 63, as is apparent from the plan view of FIG. This grid-like groove 73 leaves an island region 75.

Then, the third insulating layer 77 is formed by oxidizing the inside of the groove to form an oxide film of, for example, about 500 liters. A resist layer 85 is applied on this, and the portion which makes contact with the transistor and the capacitor is exposed and developed to be removed, and the third insulating layer 77 thereunder is removed by wet etching. This state is shown in FIG. After this, the remaining resist film 85 is peeled off.

As shown in FIG. 8C, a second conductive layer 79 such as polycrystalline silicon is formed on the entire inner surface of the groove 73. For example, with CVD, the thickness is about 2
A 000 Å non-doped polycrystalline silicon layer is deposited, and phosphorus (P) is vapor-phase-diffused to dope n-type.

Here, reactive ion etching is performed on the entire surface and the groove is
73 Second conductive layer 79 on bottom surface and island area 75 of semiconductor substrate 79
To remove. The conductive layer 79 remains only on the side surface of the groove 73. After that, the fourth insulating layer 81 is formed on the second conductive layer 79. For example, the surface of the polycrystalline silicon film is thermally oxidized or an insulating film such as a SiO ₂ film is deposited by CVD. The surface of the second conductive layer 79 is covered with the fourth insulating layer 81.

Next, a resist layer 87 is applied as shown in FIG.
The groove 73 is exposed by patterning by exposure and phenomenon, and the groove 73 is further dug by anisotropic etching using the remaining resist layer 87 as a mask to expose the conductive surface layer 71 of the support substrate 61.

As shown in FIG. 8E, a conductor is embedded in the groove 73 dug in this way to form a conductive region 83. For example, polycrystalline silicon is deposited by CVD, and phosphorus (P) is added at 18Ω /
□ About vapor phase diffusion. Then, the entire surface is etched back to remove the polycrystalline silicon on the surface.

The conductive region 83 is electrically connected to the conductive surface layer 71 of the substrate 61 and faces the second conductive layer 79 via the fourth insulating layer 81. That is, the first conductive layer 65 and the second conductive layer 79 are connected to form the information storage electrode of the capacitor, and the conductive surface layer 71 of the substrate 61 and the conductive region 83 are connected to form the counter electrode of the capacitor.

Then, a transistor is formed in each island region 75 of the semiconductor substrate 63 to complete a memory cell. For example, a polycrystalline silicon gate electrode 90 is formed on the gate insulating film, and ion implantation is performed to form a source region 91 and a drain region 92.

In this way, a semiconductor memory device in which one memory cell includes one transistor and one capacitor is formed. Since the capacitance of the capacitor formed by the first conductive layer 65 can be increased and the information storage electrode and the transistor are completely insulated and separated from the supporting substrate 61, carriers are generated in the supporting substrate 61 by the alpha ray irradiation. However, it is not easily affected by it.

FIG. 9 is a partial plan view of a semiconductor device manufactured through the steps of FIGS. 8 (A) to (F).

The island regions 75 are arranged in a matrix, and the grooves 73 extend in a grid pattern therebetween. A third insulating image 77, a second conductive layer 79, and a fourth insulating layer 81 surround the periphery of each island region 75. The third insulating layer 77 is not provided on a part of the surface of the drain region 92, where the second conductive layer 79 contacts the drain region 92. The size of one memory cell is, for example, 1.5 μm × 3.25 μm.

FIG. 10 shows a structural example in which two conductive layers are formed in the insulating layer as shown in FIG. The underlying conductive layer can be considered as the (isolated) conductive surface layer of the support substrate. Therefore, the conductive region 83 embedded in the groove 73 is a support substrate.
The conductive surface layer 95 formed on the insulating layer 94 on the supporting substrate 61 is contacted instead of the body of 61. The other points are almost the same as the configuration shown in FIG.

In the case of the structure shown in FIG. 10, the support substrate 61, which is a silicon substrate, for example, is double insulated from the information storage electrodes 65 and 79. Therefore, the soft error resistance is further increased.

FIG. 11 shows a DRAM type semiconductor device according to another embodiment of the present invention.

On a support substrate 61 made of n-type silicon, two capacitor electrode regions 97, 98 made of polycrystalline silicon sandwiching an insulating layer 99 made of SiO ₂ are arranged, and a fin-type capacitor 96. Are configured. A semiconductor substrate 63 made of p-type silicon is arranged on top of it. The semiconductor substrate 63 is divided into a large number of island regions, and each island region has
n-type source (drain) region 91, drain (source)
A region 92 is formed, and a gate electrode 90 formed of impurity-doped polycrystalline silicon is formed on the n-channel region formed of the p-type silicon substrate 63 between the regions 92. In the structure shown in the figure, one electrode region 97 of the capacitor made of polycrystalline silicon is in ohmic contact with the drain region 92 on the side surface which is penetrated through the semiconductor substrate 63 and led out upward, and one electrode region 97 of the capacitor is formed. It is electrically connected to the drain 92 of the transistor.

In the structure of FIG. 11, a large number of field effect transistors are formed in the semiconductor substrate 63, and fin type capacitors are formed in the insulating region of the SOI structure thereunder. The counter electrodes of the fin-type capacitor have a shape in which they are interdigitated with each other to realize a high capacitance. It is effective to increase the number of fins in order to further increase the capacity of the fin type capacitor. The support substrate 61 made of n-type silicon also faces the lower surface of one electrode 97 of the capacitor with the insulating layer 99 in between.
It forms part of the capacitor.

The upper surface structure of the RAM type semiconductor device shown in FIG. 11 can be similar to the upper surface structure of the semiconductor device shown in FIG. 9, for example. The width of polycrystalline silicon regions 97 and 98 on the surface of the semiconductor substrate is, for example, about 1 μm.
The polycrystalline silicon regions 97 and 98 are doped with impurities such as phosphorus (P) to have a sheet resistance of about 18Ω / □ or less.
The insulating layer 99 is, for example, a SiO ₂ film having a thickness of about 100 to 1000Å.

FIG. 12 shows a method of manufacturing the semiconductor device shown in FIG. 12 (A) to 12 (I) are cross-sectional views showing the steps of the method for manufacturing a semiconductor device.

FIG. 12A shows a step of forming a mask of an oxide film on the surface of a substrate having an SOI structure. First support layer 61 made of n-type silicon, first insulating layer 94 of SiO ₂ , first conductive layer 95 made of polycrystalline silicon doped with n-type impurities such as phosphorus (P), and SiO ₂ Second insulating layer 67, phosphorus (P)
A second conductive layer 65 made of polycrystalline silicon doped with n-type impurities and a third insulating layer 69 made of SiO ₂ are laminated. For example, each layer 94, 95, 67, 69 has a thickness of about 2000-3000Å. A semiconductor substrate 63 made of p-type silicon is arranged on the laminated structure. An oxide film 64a formed of a silicon oxide film or a phosphosilicate glass (PSG) film is formed on the surface of this semiconductor substrate 63 by CVD, for example, and a resist layer 85a is applied thereon. The resist layer is patterned to provide an opening having a width of about 1 μm, and the oxide film 64a below is patterned using this resist layer as a mask to form an oxide film mask.

FIG. 12 (B) shows that the underlying SOI structure is etched to form the first trench 73 by using the oxide film mask thus formed or a composite mask composed of the oxide film and the resist film. The step of backfilling a part with the conductive region 83 is shown. Using the oxide film mask 64a, the underlying semiconductor substrate 63, the third insulating layer 69, the second conductive layer 65, and the second insulating layer
67, the first conductive layer 95, and the first insulating layer 94 are vertically etched by RIE to expose the surface of the support substrate 61. For example,
Silicon and polycrystalline silicon are etched by RIE (reactive ion etching) using a Cl ₂ based etching gas. Further, the oxide film is formed of, for example, a fluorine-based gas (CF ₄ + CHF
Etching by RIE using ₃ mixed gas or CF ₄ + H ₂ mixed gas). In these RIEs, the etching selectivity between silicon and oxide film can be set to a value close to 10, for example. After etching is performed until the supporting substrate 61 is exposed to form the first trench 73, polycrystalline silicon 83 doped with impurities by, for example, CVD is deposited, and the first trench 73 is formed to a level slightly below the lower surface of the semiconductor substrate 63. Backfill the trench.

Instead of depositing an impurity-doped polysilicon layer, deposit an undoped polysilicon layer,
Then, impurities such as phosphorus (P) may be thermally diffused from the gas phase.

Next, as shown in FIG. 12C, the SOI structure substrate is thermally oxidized to form oxide films 77a and 77b on the exposed side surfaces of the p-type silicon semiconductor substrate 63 and the surface of the polycrystalline silicon region 83. To do. After that, the oxide film is directionally etched by RIE,
The oxide film 77b formed on the surface of the silicon region 83 on the bottom surface of the trench is removed.

Next, as shown in FIG. 12D, polycrystalline silicon doped with impurities is further deposited on the polycrystalline silicon region 83 from which the oxide film 77b on the surface is removed, and the first trench 73 is filled with polycrystalline silicon. Backfill with area 83. It is also possible to deposit non-doped polycrystalline silicon instead of depositing the impurity-doped polycrystalline silicon and then dope the impurity by vapor phase diffusion. Figure 12 (D)
In the structure, the two conductive layers formed in the SOI insulating region are connected by the polycrystalline silicon region 83 formed in the first trench.
83 extends from the surface of the n-type silicon support substrate 61 to the surface of the p-type silicon semiconductor substrate 63. Further, since the oxide film 77 is formed between the polycrystalline silicon region 83 and the semiconductor substrate 63, they are electrically insulated from each other.

Next, as shown in FIG. 12E, another oxide film mask 64b having an opening with a width of about 1 μm is formed on the surface of the semiconductor substrate 63, and the second oxide film mask 64b is used as a mask to form a second oxide film by RIE. Forming a trench 74 of. This second trench 74
Also formed by RIE vertically from the surface of the semiconductor substrate 63 to the surface of the support substrate 64. The etchant gas may be the same as that used when forming the first trench 73.

Next, as shown in FIG. 12F, etching is performed using, for example, a hydrofluoric acid aqueous solution to remove the oxide film region exposed in the second trench 74. The oxide film is removed to form the cavity 75. The etching automatically stops when the second trench 74 and the cavity 75 are entirely exposed to the silicon surface.

The case of wet etching using a hydrofluoric acid aqueous solution has been described, but isotropic etching may be performed by dry etching. In this way, the polycrystalline silicon backfill region
A structure is formed in which the polycrystalline silicon layers 65 and 95 project from 83 into the cavity.

Next, as shown in FIG. 12 (G), the surfaces of the semiconductor substrate 63 and the polycrystalline silicon regions 65, 95, 83 exposed in the second trench 74 and the cavity 75 of the structure having the cavity are, for example, It is covered with an oxide film by thermal oxidation. For example, a silicon oxide film having a thickness of 100 to 1000Å is formed by thermal oxidation. Alternatively, SiO ₂ may be deposited by CVD with an insulating film such as Si ₃ N ₄ . Thus, the second trench 74 and the cavity
The surface of 75 is entirely covered with the insulating film 77c. The surface of the semiconductor substrate 63 is also covered with the insulating film 77c.

Next, as shown in FIG. 12H, the cavity 75 and the second trench 74 are backfilled with polycrystalline silicon 83b doped with an n-type impurity such as phosphorus (P). The backfilled polycrystalline silicon 83b is etched until the side surface of the semiconductor substrate 63 is exposed,
The exposed oxide film 77c is removed by etching to remove the semiconductor substrate 63.
Expose the sides of.

Next, as shown in FIG. 12 (I), polycrystalline silicon 83b further doped with impurities is deposited to form the second trench 7
Backfill 4.

Instead of backfilling with polycrystalline silicon to the middle and etching the oxide film, the cavity 75 and the second trench 74 are filled with a host resist layer, and exposure and development are performed so that the side surface of the semiconductor substrate 63 is exposed. After removing the exposed oxide film, the buried resist region may be removed, and the doped polycrystalline silicon 83b may be deposited in the second trench 74 and the cavity 75 to be backfilled.

Also, the semiconductor substrate 63 and the doped polycrystalline silicon region 83
A host resist mask may be formed in the step of FIG. 12 (H) so as to limit the contact area of b, and the side surface of the semiconductor substrate 63 may be selectively exposed to perform etching.

13 (A) and 13 (B) show a fin-type capacitor portion of a semiconductor device according to another embodiment of the present invention.

FIG. 13 (A) shows an example of a two-layer fin structure. A first electrode 97 having two conductive layers made of doped polycrystalline silicon is formed on a supporting substrate 61 made of silicon or the like, and one doped poly-silicon layer is inserted in a nested manner between the two conductive layers. The other electrode 98 including a crystalline silicon conductive layer is formed. Since the other electrode 98 is also electrically connected to the support substrate 61, the other electrode 98 also has two layers of electrodes. A SiO ₂ film 99 is formed between the electrodes 97 and 98.

FIG. 13 (B) shows a four-layer fin structure. One electrode 97 having four conductive layers made of doped polycrystalline silicon on a support substrate 61 such as n-type silicon, and a doped polycrystalline silicon conductive material inserted in a nested manner between the four electrodes. The layer 98 and the second electrode 98 having the surface of the supporting substrate 61 are opposed to each other with the insulating layer 99 in between, and form a four-layer fin type capacitor structure.

Note that the number of stacked layers can be increased to form a capacitor structure including a larger number of layers.

The thickness of each conductive layer of the fin-type capacitor is, for example, about 2000 to 3000Å, and the thickness of the insulating layer 99 between the electrodes is
For example, 100 to 1000Å.

Instead of polycrystalline silicon, amorphous silicon, silicide such as tungsten silicide, titanium silicide, molybdenum silicide, or CVD tungsten can be used as the conductor. Further, as the insulating material, an oxide film or nitride film formed by CVD, a Ta ₂ O ₅ film formed by CVD, or the like can be used as well as SiO _{2 formed} by thermal oxidation.

Although the present invention has been described above with reference to the embodiments, the present invention is not limited thereto. For example, various changes,
It will be apparent to those skilled in the art that improvements and combinations can be made.

[Effects of the Invention] As described above, according to the present invention, it is possible to provide an SOI (semiconductor on insulator) structure with a structure in which a capacitor is built in, and increase the capacitance of the capacitor.

The soft error resistance can be increased by increasing the capacity.

Further, the information storage electrode and the transistor are completely insulated and separated from the supporting substrate. Therefore, the soft error resistance can be further increased.

[Brief description of drawings]

1 (A) to (C) are explanatory views of the principle of the present invention.
(A) and (B) are cross-sectional views of the semiconductor device, and (C) is (A).
2 is a cross-sectional view schematically showing a method of manufacturing the semiconductor device shown in FIG. 2, FIG. 2 is a cross-sectional view of a semiconductor memory cell according to the prior art, and FIGS. 3A to 3G are methods of manufacturing the semiconductor memory cell of FIG. 4 (A) to 4 (D) are cross-sectional views for explaining each step of the method for manufacturing a semiconductor device according to the embodiment of the present invention, and FIG. 5 (A) is a cross-sectional view for explaining each step. 6A to 6D are cross-sectional views for explaining each step of the method for manufacturing a semiconductor device according to another embodiment of the present invention, and FIGS. 6A to 6D are semiconductor devices according to another embodiment of the present invention. 7A to 7D are cross-sectional views for explaining each step of the method for manufacturing a semiconductor device, and FIGS. 7A to 7D are cross-sectional views for explaining each step of the method for manufacturing a semiconductor device according to another embodiment of the present invention. FIGS. 8A to 8F are views showing a method of manufacturing a semiconductor device forming a memory cell according to another embodiment of the present invention. FIG. 9 is a plan view of the semiconductor device shown in FIG. 8, FIG. 10 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention, and FIG. 11 is another view of the present invention. 12A to 12I are sectional views of the semiconductor device according to the embodiment of the present invention, and FIGS. 13A to 13B are sectional views for explaining the method for manufacturing the semiconductor device shown in FIG. 8] is a sectional view of a semiconductor device according to another embodiment of the present invention. In the figure, 1 ... Support substrate 3 ... Semiconductor substrate 5 ... First conductive layer 7 ... First insulating layer 9 ... Second insulating layer 11 ... Conductive surface layer 13 ... Groove 15 ... Island Region 16 ... Semiconductor element 17 ... Third insulating layer 19 ... Second conductive layer 21 ... Fourth insulating layer 22 ... Current terminal 23 ... Conductive region 25 ... First silicon substrate 27 ... Oxide film 29 ... Conductive layer 31 ... Insulating film 33 ... Second silicon substrate 35 ... Oxide film 40 ... Semiconductor substrate 42 ... Insulating film 44 ... Conductive film 46 ... Insulating film 48 ... Conductive film 49 ... Insulating film 50 …… Supporting substrate 52 …… Insulating film 54 …… Conductive layer 56 …… Insulating film 58 …… Conductive layer 59 …… Insulating film 61 …… Supporting substrate 63 …… Semiconductor substrate 64 …… Oxide film 65… … First conductive layer 67 …… First insulating layer 69 …… Second insulating layer 73 …… Groove 75 …… Island region 77 …… Third insulating layer 79 …… Second conductive layer 81 …… Fourth insulating layer 83 …… Conductive area 85 …… Resist layer 87 …… Gist layer 90 ...... Gate electrode 91 ...... Source region 92 ...... Drain region 94 ...... Insulating layer 95 ...... (insulation separated) conductive layer 95 ...... Capacitor 97, 98 ...... Capacitor electrode 99 ...... Capacitor Insulation layer

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical indication H01L 27/12

Claims (11)

[Claims] 1. A supporting substrate (1) having a conductive surface layer (11), and a first insulating layer (7) arranged on the supporting substrate (1).
And a first capacitor disposed on the first insulating layer (7) and forming a capacitance with the surface layer (11) with the first insulating layer (7) interposed therebetween.
A conductive layer (5) and a second insulating layer (9) disposed on the first conductive layer (5)
And a semiconductor substrate (3) arranged on the second insulating layer (9)
A means (19) for electrically connecting the first conductive layer (5) to a part of the semiconductor substrate (3); and a plurality of the first conductive layer (5) and the upper structure. A semiconductor element (16) formed in each island region (15) including a groove (13) separating the island region (15)
A semiconductor device forming an integrated circuit separated by the groove. 2. The semiconductor device according to claim 1, wherein the supporting substrate (1) includes a semiconductor substrate, a surface insulating layer disposed on the semiconductor substrate, and the conductive surface layer disposed thereon. 3. A supporting substrate (1) having a conductive surface layer (11), a first insulating layer (7) arranged on the supporting substrate, and arranged on the first insulating layer (7). And said surface layer (11)
A first conductive layer (5) forming a capacitance between the first conductive layer (5) and a second insulating layer (9) arranged on the first conductive layer (5)
And a semiconductor substrate (3) arranged on the second insulating layer (9)
And a groove (which reaches the conductive surface layer (11) from the surface of the semiconductor substrate (3) and separates the first conductive layer (5) and the semiconductor substrate (3) into a plurality of island regions (15). 13), a third insulating layer (17) formed on the side wall of the groove (13) and covering the side surface of each of the plurality of island regions (15) except the contact portion, and the island region (15). The first conductive layer (5) and the semiconductor substrate (3) in each island region (15) at each side contact portion.
And a second conductive layer (19) formed on the third insulating layer (17) on the other side surface of the island region (15), and formed on the second conductive layer (19). Fourth insulating layer (21)
And a conductive region (23) formed on the fourth insulating layer (21) to form a capacitance between the second conductive layer (19) and electrically contacting the surface layer (11). , Formed in each of the island regions (15) and having one current terminal (2
A semiconductor device having 2) a semiconductor element (16) electrically connected to the second conductive layer (19). 4. The semiconductor device according to claim 3, wherein the supporting substrate (1) includes a semiconductor substrate, a surface insulating layer disposed on the semiconductor substrate, and the conductive surface layer disposed thereon. 5. A step of forming a first insulating layer (27, 35) on at least one surface of a first semiconductor substrate (25) and at least one surface of a second semiconductor substrate (33), A step of forming a conductive film (29) and a second insulating film (31) on the first insulating film (27) of the semiconductor substrate (25), and a second insulating film (31) of the first semiconductor substrate (25) And a step of bonding the first insulating film (35) of the second semiconductor substrate (3) together. 6. The method of manufacturing a semiconductor device according to claim 5, wherein the step of forming the conductive film and the insulating film is repeated. 7. The method of manufacturing a semiconductor device according to claim 5, further comprising the step of polishing either the first semiconductor substrate (5) or the second semiconductor substrate (33) to a predetermined thickness. 8. The method of manufacturing a semiconductor device according to claim 6, further comprising the step of forming a separation groove (13) penetrating the conductive film thereunder from the surface of the semiconductor substrate (3) thinned to a predetermined thickness. 9. A supporting substrate (61) capable of providing physical support, an insulating region (99) arranged on the supporting substrate (61), and a semiconductor arranged on the insulating region (99). A semiconductor device having a capacitor structure formed in the insulating region (99) of an SOI structure having a substrate (63). 10. The first electrode, wherein the capacitor structure includes a plurality of conductive layers arranged in the insulating region (99) and a conductive region connecting the conductive layers, and the first electrode. The insulating region (9
9. A semiconductor device according to claim 9, further comprising a second electrode including a conductive layer that is inserted through a part of 9) and forms a capacitor therebetween. 11. A support substrate (61) having an insulating region containing a plurality of conductive layers, and a semiconductor substrate (63) on the insulating region.
And a step of forming a first trench reaching at least a second conductive layer from the top in the insulating region from the surface of the semiconductor substrate of the SOI structure; Filling with a material, forming a second trench that reaches from the semiconductor surface to at least an insulating region directly above the lowermost conductive layer that the first trench reaches, and exposing in the second trench A semiconductor device comprising: a step of etching the formed insulating region from the opening of the second trench; a step of forming an insulating layer on the surface of the exposed conductive material; and a step of filling the inside of the second trench with a conductive material. Manufacturing method.