JPS6399433U - - Google Patents
Info
- Publication number
- JPS6399433U JPS6399433U JP19640586U JP19640586U JPS6399433U JP S6399433 U JPS6399433 U JP S6399433U JP 19640586 U JP19640586 U JP 19640586U JP 19640586 U JP19640586 U JP 19640586U JP S6399433 U JPS6399433 U JP S6399433U
- Authority
- JP
- Japan
- Prior art keywords
- analog signal
- analog
- digital
- circuit
- divide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Analogue/Digital Conversion (AREA)
Description
第１図は本考案のデジタル―アナログ変換器の
一実施例の構成を示す図、第２図は従来のデジタ
ル―アナログ変換器の構成を示す図である。
１……入力データ、２……第１のデジタル―ア
ナログ変換回路、３……第２のデジタル―アナロ
グ変換回路、４……レベル調節回路、５……加算
回路。
FIG. 1 is a diagram showing the configuration of an embodiment of the digital-to-analog converter of the present invention, and FIG. 2 is a diagram showing the configuration of a conventional digital-to-analog converter. 1... Input data, 2... First digital-analog conversion circuit, 3... Second digital-analog conversion circuit, 4... Level adjustment circuit, 5... Addition circuit.
Claims (1)
ジタル―アナログ変換器。 (イ) ｎビツトの入力データ ［Ｄｎ‐１，Ｄｎ‐２……Ｄ１，Ｄ０］ を所定の桁ｍにおいて分割し、当該分割した（ｎ
−ｍ）ビツトの上位データ ［Ｄｎ‐１，Ｄｎ‐２……Ｄｍ＋１，Ｄｍ］ を第１のアナログ信号に変換する第１のデジタル
―アナログ変換回路２。 (ロ) 上記分割したｍビツトの下位データ ［Ｄｍ‐１，Ｄｍ‐２……Ｄ１，Ｄ０］ を第２のアナログ信号に変換する第２のデジタル
―アナログ変換回路３。 (ニ) 上記第２のアナログ信号を１／２ｎ‐ｍ倍
するレベル調節回路４。 (ホ) 上記第１のアナログ信号とレベル調節回路
ｌ−２の出力信号とを加算して出力アナログ信号
を出力する加算回路５。[Scope of Claim for Utility Model Registration] A digital-to-analog converter characterized by having the following configuration requirements. (b) Divide n-bit input data [Dn-1, Dn-2...D1, D0] at a predetermined digit m, and divide the divided (n
-m) A first digital-to-analog conversion circuit 2 that converts the upper bit data [Dn-1, Dn-2...Dm+1, Dm] into a first analog signal. (b) A second digital-to-analog conversion circuit 3 that converts the divided m-bit lower-order data [Dm-1, Dm-2...D1, D0] into a second analog signal. (d) A level adjustment circuit 4 that multiplies the second analog signal by 1/2 nm . (E) An adder circuit 5 that adds the first analog signal and the output signal of the level adjustment circuit l-2 and outputs an output analog signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19640586U JPS6399433U (en) | 1986-12-19 | 1986-12-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19640586U JPS6399433U (en) | 1986-12-19 | 1986-12-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6399433U true JPS6399433U (en) | 1988-06-28 |
Family
ID=31155198
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19640586U Pending JPS6399433U (en) | 1986-12-19 | 1986-12-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6399433U (en) |
-
1986
- 1986-12-19 JP JP19640586U patent/JPS6399433U/ja active Pending
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