JPS6413144U - - Google Patents

Info

Publication number
JPS6413144U
JPS6413144U JP10542987U JP10542987U JPS6413144U JP S6413144 U JPS6413144 U JP S6413144U JP 10542987 U JP10542987 U JP 10542987U JP 10542987 U JP10542987 U JP 10542987U JP S6413144 U JPS6413144 U JP S6413144U
Authority
JP
Japan
Prior art keywords
integrated circuit
heat sink
chip
hole
bonded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10542987U
Other languages
English (en)
Other versions
JPH0610718Y2 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP10542987U priority Critical patent/JPH0610718Y2/ja
Publication of JPS6413144U publication Critical patent/JPS6413144U/ja
Application granted granted Critical
Publication of JPH0610718Y2 publication Critical patent/JPH0610718Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Combinations Of Printed Boards (AREA)
  • Wire Bonding (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Metal Substrates For Printed Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Description

【図面の簡単な説明】
第１図は本考案の一実施例を断面で示すもので
第２図の−線に沿う断面図、第２図は第１図
のものの平面図、第３図ａ，ｂは接合前の状態を
示す平面図、第４図ａ，ｂは第３図のそれぞれａ
，ｂ線に沿つた断面図である。 １……放熱板、２……接着剤、３……切欠き、
４……基板、５……ＩＣチツプ、６……ワイヤ、
７……端子。

Claims (1)

    【実用新案登録請求の範囲】
  1. 良熱伝導材からなる放熱板の上面に一部に孔ま
    たは切欠きを設けた積層状態の基板を接合し、該
    基板の前記孔または切欠きにＩＣチツプをその下
    面が前記放熱板に接するようにして挿入し、該Ｉ
    Ｃチツプのボンデイングパツドと前記積層状態の
    各基板との間をボンデイングワイヤにより接続し
    た集積回路素子を２枚製作し、該２枚の集積回路
    素子を前記放熱板の部分において背中合せに接着
    したことを特徴とする集積回路素子の保持構造。
JP10542987U 1987-07-09 1987-07-09 集積回路素子の保持構造 Expired - Lifetime JPH0610718Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10542987U JPH0610718Y2 (ja) 1987-07-09 1987-07-09 集積回路素子の保持構造

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10542987U JPH0610718Y2 (ja) 1987-07-09 1987-07-09 集積回路素子の保持構造

Publications (2)

Publication Number Publication Date
JPS6413144U true JPS6413144U (ja) 1989-01-24
JPH0610718Y2 JPH0610718Y2 (ja) 1994-03-16

Family

ID=31338034

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10542987U Expired - Lifetime JPH0610718Y2 (ja) 1987-07-09 1987-07-09 集積回路素子の保持構造

Country Status (1)

Country Link
JP (1) JPH0610718Y2 (ja)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019009466A (ja) * 2014-11-20 2019-01-17 日本精工株式会社 電子部品搭載用放熱基板
JP2024547003A (ja) * 2021-12-17 2024-12-26 メイコム テクノロジー ソリューションズ ホールディングス インコーポレイテッド マルチタイプ集積型パッシブデバイス（ｉｐｄ）構成要素及びこれを実施するデバイス及びプロセス
US12417966B2 (en) 2021-12-17 2025-09-16 Macom Technology Solutions Holdings, Inc. IPD components having SiC substrates and devices and processes implementing the same
US12620530B2 (en) 2022-09-23 2026-05-05 Wolfspeed, Inc. Device and process for implementing silicon carbide (SiC) surface mount devices

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019009466A (ja) * 2014-11-20 2019-01-17 日本精工株式会社 電子部品搭載用放熱基板
JP2019009465A (ja) * 2014-11-20 2019-01-17 日本精工株式会社 電子部品搭載用放熱基板
JP2019041110A (ja) * 2014-11-20 2019-03-14 日本精工株式会社 電子部品搭載用放熱基板
JP2024547003A (ja) * 2021-12-17 2024-12-26 メイコム テクノロジー ソリューションズ ホールディングス インコーポレイテッド マルチタイプ集積型パッシブデバイス（ｉｐｄ）構成要素及びこれを実施するデバイス及びプロセス
US12417966B2 (en) 2021-12-17 2025-09-16 Macom Technology Solutions Holdings, Inc. IPD components having SiC substrates and devices and processes implementing the same
US12620530B2 (en) 2022-09-23 2026-05-05 Wolfspeed, Inc. Device and process for implementing silicon carbide (SiC) surface mount devices

Also Published As

Publication number Publication date
JPH0610718Y2 (ja) 1994-03-16

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