JPS6420637A - Formation of wiring - Google Patents
Formation of wiringInfo
- Publication number
- JPS6420637A JPS6420637A JP17685787A JP17685787A JPS6420637A JP S6420637 A JPS6420637 A JP S6420637A JP 17685787 A JP17685787 A JP 17685787A JP 17685787 A JP17685787 A JP 17685787A JP S6420637 A JPS6420637 A JP S6420637A
- Authority
- JP
- Japan
- Prior art keywords
- film
- resist
- pattern
- contact hole
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015572 biosynthetic process Effects 0.000 title 1
- 239000002184 metal Substances 0.000 abstract 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 239000000758 substrate Substances 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
PURPOSE:To delete the steps of resist coating, removing resist, and prebaking and to enhance the efficiency of treatment by employing a common mask for forming both a contact hole and an upper layer wiring pattern. CONSTITUTION:A metal layer 2 is formed on a substrate 1 formed with a semiconductor element, an insulating SiO2 film 3 is deposited, the film 3 is coated with positive type resist 4, prebaked, then exposed to form a contact hole to the film 2 with a far infrared ray, developed and postbaked to obtain a desired resist pattern. With the resist 4 as a mask the film 3 is etched to form a contact hole 3', thereby partly exposing the film 2. Then, an exposure for a pattern for forming a metal film as upper layer wirings is similarly performed to obtain a resist pattern, and a metal film 5 is deposited on the whole surface. Subsequently, the resist 4 and the metal film are removed to obtain a predetermined pattern film 5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17685787A JPS6420637A (en) | 1987-07-15 | 1987-07-15 | Formation of wiring |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17685787A JPS6420637A (en) | 1987-07-15 | 1987-07-15 | Formation of wiring |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6420637A true JPS6420637A (en) | 1989-01-24 |
Family
ID=16021037
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17685787A Pending JPS6420637A (en) | 1987-07-15 | 1987-07-15 | Formation of wiring |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6420637A (en) |
-
1987
- 1987-07-15 JP JP17685787A patent/JPS6420637A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| DE3584461D1 (en) | METHOD AND DEVICE FOR PRODUCING CONDUCTIVE PATTERNS ON A SUBSTRATE. | |
| EP0095209A3 (en) | Method of forming a resist mask resistant to plasma etching | |
| EP0304077A3 (en) | Method of forming a fine pattern | |
| JPS57149752A (en) | Structure of multilayer wiring | |
| JPS5568655A (en) | Manufacturing method of wiring | |
| JPS5490971A (en) | Pattern forming method | |
| JPS5527639A (en) | Photo-resist pattern forming method | |
| JPS5732653A (en) | Manufacture of semiconductor device | |
| JPS57187954A (en) | Formation of buried wiring | |
| JPS54162462A (en) | Semiconductor device and its manufacture | |
| JPS5749230A (en) | Forming method for electrode | |
| JPS5527637A (en) | Photo-resist-pattern forming method | |
| JPS57102051A (en) | Manufacture of semiconductor device | |
| JPS57118641A (en) | Lifting-off method | |
| JPS5555546A (en) | Method of wiring semiconductor device | |
| JPS5785247A (en) | Formation of fetch electrode | |
| JPS5558374A (en) | Etching method | |
| JPS5656654A (en) | Manufacture of semiconductor device | |
| JPS57145330A (en) | Manufacture of semiconductor device | |
| JPS57101668A (en) | Etching method | |
| JPS6489540A (en) | Formation of wiring pattern | |
| JPS5743425A (en) | Forming method for fine pattern | |
| JPS57102025A (en) | Manufacture of semiconductor device | |
| JPS54154981A (en) | Manufacture of semiconductor device | |
| JPS5558547A (en) | Wiring |