JPS642299B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a power line carrier control device used for remote monitoring and control.

FIG. 1 shows a schematic configuration of a general power line carrier control device, in which a transmitter 2 transmits a control signal as a carrier wave signal superimposed on a power line 1, a receiver 3 receives the control signal, and controls a load 5. Furthermore, the state of the load 5 is monitored on the transmitter 2 side based on the reply signal from the receiver 3. Figures 4 and 5 show examples of control signals, where a is a 0 cross pulse and b is a zero cross pulse.
is a control signal pulse, and c is a waveform diagram of a control signal based on a carrier wave B superimposed on a power supply wave A. In this example, one bit of the control signal is assigned to one period of a 0-cross pulse, and the 0-cross pulse The falling edge of is divided into four sections, and depending on whether there is a carrier wave in each divided section, (0101) is the start mark, (0111)
data “1”, (0100) data “0”, (0110)
are assigned to each end mark. Figure 5 shows an example of the configuration of a control signal. In this example, the control signal consists of 32 bits, including 1 bit for a start mark, 1 bit for a blank, 4 bits for a mode, and 1 bit for an address. It consists of 4 bits for address 2, 4 bits for address 3, 4 bits for control code, 4 bits for checksum, 1 bit for blank, 4 bits for reply period, and 1 bit for end mark, for a total of 32 bits. ing.

Here, to briefly explain the meaning of each control signal, the start mark indicates the beginning of the control signal, and the blank is assigned data 0, which is a dummy signal. The mode indicates the load control mode; (0000) turns on the load, (0001) turns off the load, and (0100) checks the load status. Addresses 1 to 3 indicate channels, and the receiver 3 of any channel is selectively called by this data. The control code uses (1000) data as a dummy signal. Also, the checksum is used to determine whether the signal has been transmitted correctly from the transmitter 2 to the receiver 3, and during the reply period, the receiver 3 returns the load status (on or off) to the transmitter 2. At this time, the receiver 3 returns a signal when the load is on (1111) and a signal when the load is off (0000). The end mark signals the end of the control signal. Above 5th
The contents of the control signals shown in the figure are clearly just one example.

Next, an example of the configuration of the receiver 2 will be explained with reference to the block diagram shown in FIG. In the circuit shown in FIG. 6, a modem 6 modulates and demodulates a carrier signal through an interface between a digital circuit and an analog circuit, and a reply data creation section 7 changes the state of the load 5 (on or off) according to the control signal from the transmitter 2. OFF) to the transmitter 2. The frequency verification section 8 counts the carrier signal frequency and verifies the presence or absence of the carrier signal during a predetermined verification period, thereby reproducing the control signal pulse shown in FIG. 4b.

The 0-cross detection section 9 detects the 0-cross point of the power supply voltage and generates a 0-cross pulse, and the timing signal generation section 10 generates signals and carriers for timing all the circuits shown in the block diagram of FIG. generate a signal. Next, the received data reproducing section 11
reproduces the start mark, data "1", data "0", and end mark based on the signal tested by the frequency testing section 8. The reference signal generation section 12 generates a reference signal required by the timing signal generation section 10, the address setting section 13 sets the address (channel) of the receiver 3, and the address determination section 14 sets the address of the received control signal and its address. It is compared with the address set in the receiver 3 to determine whether they match. Mode determination section 15
determines the mode of the received control signal. Thus, the output section 16 operates according to the outputs of the mode determination section 15 and the address determination section 14, and
When the address (channel) of the received signal matches your address (channel),
Based on the mode data and control code data,
It outputs a control output that turns the load 5 on or off. The control code determination section 17 determines whether the control code is (1000), and outputs the outputs of the address determination section 14 and the mode determination section 15 to the output section 16 at this time.

Next, an example of the configuration of the transmitter 2 will be explained using the block diagram shown in FIG. In the figure, the modem 17 is equivalent to that of the receiver 3, and the transmission data creation section 18
creates a control signal based on signals from the switch input section 19 and the received data reproducing section 21. The switch input section 19 converts the signal of the switch 22 into a digital signal, and the transmission data creation section 18 converts the signal from the switch 22 into a digital signal and generates an on control signal, an off control signal, and a confirmation control signal.
Outputs a signal to. The frequency verification section 23 is the receiver 3
The switch 22 is an externally provided switch for issuing load control commands.
0 cross detection section 24, timing signal generation section 25
are equivalent to the corresponding circuit sections of the receiver 3, and the received data reproducing section 21 is the same as the frequency verification section 2.
Based on the results verified in step 3, it reproduces the start mark, data “1”, data “0”, and end mark, as well as the control signal it is transmitting.
The control signal is compared with the received control signal, and if they do not match, a retransmission request signal is output to the transmission data creation section 18. The reference signal generating section 26 is equivalent to that in the receiver 3, and the address setting section 27 includes:
The address (channel) of this transmitter 2 is set. The address latch 28 latches the address sent by itself, and the reply data determination section 29 determines the reply signal from the receiver 3 and determines whether the load 5 is in the on state or the off state. do. The latch 20 also latches the load state connected to the receiver 3 and the address of the receiver 3 at the same time. Thus, the display section 30 receives the output of the latch 20 and displays the on/off state of the load 5 connected to the receiver 3.

Thus, in the conventional example described above, first, the receiver 3
In accordance with the control signal sent from the transmitter 2, the modem 6 demodulates the carrier signal riding on the power supply waveform in synchronization with the zero cross pulse, and the frequency verification section 8 counts the frequency of the carrier signal. Then, it is verified where the carrier signal is located between the falling edge and the falling edge of the 0 cross pulse. Next, the received data reproducing section 11 classifies and reproduces the start mark, data "1", data "0", and end mark based on the signal from the frequency verification section 8. When the address determining unit 14 determines that the address set for itself matches the address of the received control signal, the receiver 3 transmits the signal via the mode determining unit 15 and the control code determining unit 17. , load 5
An output for controlling is outputted from the output unit 16,
Furthermore, reply data to the transmitter 2 is created by the reply data creation section 7 and sent back through the modem 6. On the other hand, in the transmitter 2, when the switch 22 is pressed, a corresponding control signal is created in the transmission data creation section 18, and the control signal is transmitted to the receiver 3 through the modem 6. At this time, if the receiver is performing a receiving operation at the same time and the data it sent and the data it received are different, it immediately stops transmitting and starts transmitting again from the beginning after a certain period of time. If the control signal is correctly transmitted to the receiver 3, the receiver 3 returns a reply signal as described above. Therefore, the transmitter 2 stores the reply signal data together with the address in the latch 20, and displays the status of the load 5 on the display section 30. As described above, in the conventional system described above, the transmitter 2 can control the receiver 3 and at the same time monitor its status.

By the way, in the power line transport control device as described above, the most important thing to ensure the normal operating state of the system is noise countermeasures. Therefore, in the receiver 3 and transmitter 2 shown in the block diagrams of FIGS. 6 and 7, a method is used to detect the presence or absence of a carrier wave by counting the number of carrier signals. When frequencies in a certain range are counted a certain number of times, it is determined that the carrier signal is present. However, in this type of system, if the frequency of the carrier signal is lowered in order to extend the transmission distance of the control signal, the frequency count number will also decrease at the same time, so the margin of the count number with respect to the carrier frequency (for example, ± If the ratio itself is the same as before the carrier frequency was lowered, there is a problem that the count number will be small. In other words, if the number of counts at the initial carrier frequency is 120 and the margin is set to 108 to 132 with a margin of ±10%, the number of counts will be 12 when the carrier frequency is lowered to 1/10.
The margin of ±10% becomes 11 to 13, resulting in an extremely narrow numerical range, making stable and accurate carrier wave verification extremely difficult.

Therefore, in order to solve this problem, the frequency count period can be expanded by lowering the carrier frequency, dividing the frequency of the 0-cross pulse, and dividing the frequency of the reference signal as well. In other words, if the carrier frequency is divided by 1/n, the 0 cross pulse and the reference signal are also divided by 1/n.
All you have to do is divide the frequency. A block diagram of the circuit of the receiver 3 improved in this way is shown in FIG. This circuit in Figure 8 has two 1/n frequency dividers 3 in the circuit in Figure 6.
1 and 32, and if the circuit shown in Fig. 8 is used, a constant frequency count can always be obtained and a receiver that is resistant to noise can be obtained, and the transmitter 2 can be obtained in the same way.

However, in a circuit like the one shown in FIG. 8, another problem arises. By dividing the 0 cross pulse by 1/n, the transmitter 2
There is a problem that synchronization may not be achieved between the receiver 3 and the receiver 3. In other words, the waveforms obtained when the frequency of the 0 cross pulse is divided by 2 are shown in FIGS. or 1/
Depending on the initial state of a counter that divides the frequency by 2, etc., the fall timing of the 1/2 frequency divided pulse, which is obtained by dividing the 0 cross pulse by 1/2, may differ from each other. If the falling timings are different between the transceivers 2 and 3, a problem arises in which signals cannot be transmitted and received. Here, in FIGS. 2 and 3, a is the power supply voltage waveform, and b is 0.
The cross pulse waveform and c indicate the 1/2 frequency divided pulse waveform, respectively.

The present invention has been provided in view of the above points, and even when the carrier frequency is divided by 1/n for the purpose of enabling long-distance transmission of control signals, stable and accurate signal transmission is possible. It is an object of the present invention to provide a power line transport control system that is capable of transmitting and receiving signals, and that also prevents the transmission and reception of signals from becoming impossible due to synchronization failure between transmitters and receivers.

An embodiment of the present invention will be described in detail below with reference to the drawings.
FIG. 9 shows a configuration example of a transmitter 2 according to an embodiment of the present invention, in which two 1/n frequency dividers 33 and 34 are added to the transmitter 2 of the conventional example shown in FIG. In addition, the carrier frequency is set to 1/n of that of the conventional example shown in FIG. In addition, the timing generation circuit 25 converts the 0 cross pulse to 1/n
(n-1) types of 1/n fractions from each division stage output of 1/2 frequency division, 1/3 frequency division, ..., 1/n frequency division in the process of 1/n frequency division by the frequency divider 33 create a frequency pulse,
The transmission data creation section 18 sequentially and repeatedly transmits control signals in synchronization with the 1/n frequency divided pulses. Note that the reason why there are (n-1) types of 1/n frequency division pulses is that 1/1 frequency division is excluded.

Thus, the circuit according to the embodiment shown in FIG. 9 operates almost in the same way as the conventional circuit shown in FIG. In order to enable , 0 cross pulse to 1/n
In the process of frequency division, 1/2 frequency division, 1/3 frequency division, etc.
It is created from the output of each frequency division stage of 1/n frequency division (n-
1) When a control signal is sequentially and repeatedly transmitted in synchronization with each of the types of 1/n frequency-divided pulses, the fall timing of each of the (n-1) types of 1/n frequency-divided pulses is from the power-on timing to the 1/n frequency-divided pulse. /n frequency divider 33
Since they differ depending on the initial state of the 1/2 frequency division counter, the transmitter/receiver 2 and 3 can be synchronized using one of (n-1) types of 1/n frequency division pulses. It is a point. Therefore, when this synchronization is achieved and the control signal is normally received by the receiver 3, a return signal from the receiver 3 is latched in the latch 20. As the receiver 3 for the transmitter 2 described above, the circuit shown in FIG. 8 can be used as is. Thus, in the embodiment of FIG. 9, by dividing each of the carrier frequency, zero cross pulse, and circuit reference signal to 1/n, long-distance transmission of control signals and reliability against noise can be achieved. However, if the 0 cross pulse is simply divided by 1/n, it cannot be said that both transmitters and receivers are synchronized to the same 1/n divided pulse. 2 is such that the control signal is transmitted to the receiver 3 in synchronization with the 1/n frequency divided pulse in all cases, even if the receiver 3 is synchronized with the same 1/n frequency divided pulse as the transmitter 2. Control and monitoring is always possible even if the system is not in use.

FIG. 10 shows a configuration example of another embodiment of the present invention. In the circuit of the embodiment of FIG. 10, the output of the latch 20 is different from that of the circuit of the embodiment of FIG. 9. is the transmission data creation section 18 and the display section 3
0 and the reply signal from the receiver 3 is latched in the latch 20, the operation of the transmission data creation section 18 is immediately stopped, and the repeated transmission of the control signal is stopped.

Thus, in the circuit of the embodiment shown in FIG. 10, the circuit of the embodiment shown in FIG.
The control signal was sent out in synchronization with all of the first 1/n frequency divided pulses, but until the receiver 3 received the signal normally and sent back the response signal. is operated in the same manner as in the embodiment of FIG. 9, and when a reply signal is received from the receiver 3, a control signal to be sent out in synchronization with the falling edge of the 1/n frequency division pulse created thereafter. I have set it to stop replying to. That is, if a reply signal is received from the receiver 3 when the transmitter 2 sends out the control signal in synchronization with the second 1/n frequency divided pulse, the signals from the third to the n-1st This means that the transmission of the control signal that should be sent in synchronization with the 1/n frequency-divided pulse is stopped. Therefore, in the embodiment of FIG. 10, the transmitter 2 does not send the control signal in synchronization with the 1/n frequency divided pulse in all cases, but in turn sends the 1/n frequency divided pulse in each case. It sends a control signal in synchronization with the frequency-divided pulse and stops transmission when a reply is received from the receiver 3, which has the effect of shortening the signal transmission time, so the line is used for a long time. This eliminates interference with control between other transceivers.

Since the present invention is configured as described above, it is possible to perform frequency verification using a frequency counting method that is resistant to noise and has a large margin, even though long-distance transmission of control signals is possible. Moreover, it has the effect of preventing inability to transmit and receive control signals due to synchronization failure between the transmitter and receiver.

[Brief explanation of the drawing]

Fig. 1 is a schematic block diagram of a general power line transfer control device, Figs. 2 a to c and Figs. 3 a to c are explanatory diagrams showing that two different types of 1/2 frequency division pulses are generated, and Fig. 4 Figures a to c are explanatory diagrams of waveforms of control signals for 0 cross pulses, Figure 5 is a configuration diagram of control signals, Figure 6 is a block diagram of a conventional receiver, Figure 7 is a block diagram of the same transmitter as above, FIG. 8 is a block diagram of a long distance transmission type receiver, FIG. 9 is a block diagram of a transmitter according to one embodiment of the present invention, and FIG. 10 is a block diagram of a transmitter according to another embodiment of the present invention. , 1 is a power line, 2 is a transmitter, and 3 is a receiver.

Claims (1)

[Claims] 1 A carrier signal is transmitted and received between a transmitter and a receiver via a power line, and a 1/n frequency-divided pulse is obtained by dividing a 0-cross pulse obtained from a power supply voltage waveform to 1/n. In a power line carrier control device that performs remote control using a synchronization signal, 1/2 frequency division, 1/3 frequency division, and
..., a power line characterized by sequentially and repeatedly transmitting control signals in synchronization with (n-1) types of 1/n frequency-divided pulses generated from the outputs of each 1/n frequency division stage. Conveyance control device. 1 of (n-1) types created from the outputs of each division stage of 1/2 division, 1/3 division, ..., 1/n division in the process of dividing 20 cross pulses by 1/n. A control signal is sequentially and repeatedly transmitted in synchronization with each /n frequency divided pulse, and when the control signal is normally received by the receiver and the return signal is sent back, the 1/n frequency at that time is
2. The power line carrier control device according to claim 1, wherein the repeated transmission of the control signal in synchronization with the 1/n frequency division pulse generated after the frequency division pulse is stopped.