JPS6423169A - Pulse width distribution state detecting circuit - Google Patents

Pulse width distribution state detecting circuit

Info

Publication number
JPS6423169A
JPS6423169A JP17872387A JP17872387A JPS6423169A JP S6423169 A JPS6423169 A JP S6423169A JP 17872387 A JP17872387 A JP 17872387A JP 17872387 A JP17872387 A JP 17872387A JP S6423169 A JPS6423169 A JP S6423169A
Authority
JP
Japan
Prior art keywords
memory
pulse width
circuit
measurement
pulse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17872387A
Other languages
Japanese (ja)
Inventor
Hideko Tanaka
Masuo Hanawaka
Kenta Mikuriya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yokogawa Electric Corp
Original Assignee
Yokogawa Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yokogawa Electric Corp filed Critical Yokogawa Electric Corp
Priority to JP17872387A priority Critical patent/JPS6423169A/en
Publication of JPS6423169A publication Critical patent/JPS6423169A/en
Pending legal-status Critical Current

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  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE:To obtain the frequency distribution of pulse width values at a high speed with small memory capacity by providing a pulse width measuring circuit, a memory, a timing control circuit, etc. CONSTITUTION:The pulse with measuring circuit 1 starts measuring pulse width with a command Ps from the timing control circuit 51, generate an end pulse Pe at the end of measurement, and outputs its measurement output Mi to the address bus of the memory 3. Then the circuit 51 generates a read/write signal R/W and accesses the memory 3 by using the output Mi as address information. Further, the contents of a specified address of the memory 3 are read out to a +1 arithmetic circuit 52, increased by 1, and stored again in the same address. Thus, the output Mi is used as the address information to access the memory 3, whose contents are increased by one in order to record the cumulative frequency of each pulse width value in the memory 3 directly. Therefore, the contents of the memory 3 are read out at the end of the measurement in the increasing order of the pulse width values to obtain the frequency distribution of the pulse width values.
JP17872387A 1987-07-17 1987-07-17 Pulse width distribution state detecting circuit Pending JPS6423169A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17872387A JPS6423169A (en) 1987-07-17 1987-07-17 Pulse width distribution state detecting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17872387A JPS6423169A (en) 1987-07-17 1987-07-17 Pulse width distribution state detecting circuit

Publications (1)

Publication Number Publication Date
JPS6423169A true JPS6423169A (en) 1989-01-25

Family

ID=16053443

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17872387A Pending JPS6423169A (en) 1987-07-17 1987-07-17 Pulse width distribution state detecting circuit

Country Status (1)

Country Link
JP (1) JPS6423169A (en)

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