JPS642399A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS642399A JPS642399A JP62158578A JP15857887A JPS642399A JP S642399 A JPS642399 A JP S642399A JP 62158578 A JP62158578 A JP 62158578A JP 15857887 A JP15857887 A JP 15857887A JP S642399 A JPS642399 A JP S642399A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- cap
- metallic layer
- holes
- onto
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W42/00—Arrangements for protection of devices
- H10W42/20—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
- H10W70/68—Shapes or dispositions thereof
- H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
PURPOSE: To obtain a positive magnetic shielding effect by previously bringing lead pins set up around a semiconductor element into contact with a metallic layer formed onto the surface of a substrate made of plastics and a cap made of a metal when the element is mounted onto the rear of the substrate and the rear of the substrate including the element is covered with the cap through a sealing resin frame.
CONSTITUTION: A recessed section is shaped to the rear of a substrate 1 made of plastics, a semiconductor element 8 is buried into the recessed section, and terminals fitted to the semiconductor element 8 are connected to a metallic layer surrounding the element 8 by using bonding wires 9. The whole rear including the element 8 is hermetically sealed with a cap 5 made of a metal through a resin sealing frame 6, through-holes 11 are bored penetrated through the metallic layer 2 applied onto the surface of the substrate 1 and the cap 5, lead pins 3 are inserted into the through-holes 11 while being protruded from the rear of the substrate 1, and fixed to a metallic layer 12 on the rear of the cap 5 by employing solder 4, and the pins 3 are connected to a power supply. Accordingly, the metallic layers are shaped onto the surface and rear of the substrate 1 and connected by the lead pins 3 through the through-holes 11, thus completing electromagnetic shielding to the element 8.
COPYRIGHT: (C)1989,JPO&Japio
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62158578A JPH0775279B2 (en) | 1987-06-25 | 1987-06-25 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62158578A JPH0775279B2 (en) | 1987-06-25 | 1987-06-25 | Semiconductor device |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JPH012399A JPH012399A (en) | 1989-01-06 |
| JPS642399A true JPS642399A (en) | 1989-01-06 |
| JPH0775279B2 JPH0775279B2 (en) | 1995-08-09 |
Family
ID=15674750
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62158578A Expired - Lifetime JPH0775279B2 (en) | 1987-06-25 | 1987-06-25 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0775279B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5323533A (en) * | 1991-03-26 | 1994-06-28 | Thomson-Csf | Method of producing coaxial connections for an electronic component, and component package |
| EP0667643A1 (en) * | 1994-01-20 | 1995-08-16 | Tokin Corporation | Electromagnetic interference suppressing body having low electromagnetic transparency and reflection, and electronic device having the same |
| US5923540A (en) * | 1993-11-30 | 1999-07-13 | Fujitsu Limited | Semiconductor unit having semiconductor device and multilayer substrate, in which grounding conductors surround conductors used for signal and power |
| EP1089336A3 (en) * | 1999-09-22 | 2005-07-20 | Lucent Technologies Inc. | Integrated circuit packages with improved EMI characteristics |
| JP2008026079A (en) * | 2006-07-19 | 2008-02-07 | Matsushita Electric Works Ltd | Infrared detector and its manufacturing method |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59186397A (en) * | 1983-04-06 | 1984-10-23 | 三菱電機株式会社 | Hybrid integrated circuit |
-
1987
- 1987-06-25 JP JP62158578A patent/JPH0775279B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59186397A (en) * | 1983-04-06 | 1984-10-23 | 三菱電機株式会社 | Hybrid integrated circuit |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5323533A (en) * | 1991-03-26 | 1994-06-28 | Thomson-Csf | Method of producing coaxial connections for an electronic component, and component package |
| US5923540A (en) * | 1993-11-30 | 1999-07-13 | Fujitsu Limited | Semiconductor unit having semiconductor device and multilayer substrate, in which grounding conductors surround conductors used for signal and power |
| EP0667643A1 (en) * | 1994-01-20 | 1995-08-16 | Tokin Corporation | Electromagnetic interference suppressing body having low electromagnetic transparency and reflection, and electronic device having the same |
| US5864088A (en) * | 1994-01-20 | 1999-01-26 | Tokin Corporation | Electronic device having the electromagnetic interference suppressing body |
| US6448491B1 (en) | 1994-01-20 | 2002-09-10 | Tokin Corporation | Electromagnetic interference suppressing body having low electromagnetic transparency and reflection, and electronic device having the same |
| EP1089336A3 (en) * | 1999-09-22 | 2005-07-20 | Lucent Technologies Inc. | Integrated circuit packages with improved EMI characteristics |
| JP2008026079A (en) * | 2006-07-19 | 2008-02-07 | Matsushita Electric Works Ltd | Infrared detector and its manufacturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0775279B2 (en) | 1995-08-09 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| EXPY | Cancellation because of completion of term |