JPS56105656A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS56105656A
JPS56105656A JP853280A JP853280A JPS56105656A JP S56105656 A JPS56105656 A JP S56105656A JP 853280 A JP853280 A JP 853280A JP 853280 A JP853280 A JP 853280A JP S56105656 A JPS56105656 A JP S56105656A
Authority
JP
Japan
Prior art keywords
ceramic
chip
external
substrate
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP853280A
Other languages
Japanese (ja)
Other versions
JPS6041858B2 (en
Inventor
Katsuhiko Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP55008532A priority Critical patent/JPS6041858B2/en
Publication of JPS56105656A publication Critical patent/JPS56105656A/en
Publication of JPS6041858B2 publication Critical patent/JPS6041858B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/10—Containers or parts thereof
    • H10W76/12—Containers or parts thereof characterised by their shape
    • H10W76/15—Containers comprising an insulating or insulated base
    • H10W76/157—Containers comprising an insulating or insulated base having interconnections parallel to the insulating or insulated base
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To enable a mounting in high density to be preclised by a method wherein steps are formed on an external side wall of a layer-built chip-carrier type container composed of a metallized layer mounted on a ceramic plate, and an external electrode is arranged. CONSTITUTION:Ceramic frames 11b, 12b are piled on a ceramic substrate 1b to form the steps, and the metallized layers of W are formed on a junction pad 5b, an attaching means 3b of IC chip 2, from the pade 5b to the external electrode 8 through the ceramic layer-built 7b and further, a fitting means of a sealing ring 6b. A heatsink 13b is fitted on the reverse of a package as required. The chip 2b is applied a wiring 4b and hermetically sealed with a cap 9b. Moreover, a circuit substrate 14b is fitted with the package using the external terminal 8b. In the event, with a gap between a fitting hole and the external diameter made of the order of 0.2mm., the position fitting for soldering is made easily. The device allowing the epoxy glass and polyamide resin to be used on the substrate 14b, being low in the heat resistance and having the high density mounting in high reliability can be obtained.
JP55008532A 1980-01-28 1980-01-28 semiconductor equipment Expired JPS6041858B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55008532A JPS6041858B2 (en) 1980-01-28 1980-01-28 semiconductor equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55008532A JPS6041858B2 (en) 1980-01-28 1980-01-28 semiconductor equipment

Publications (2)

Publication Number Publication Date
JPS56105656A true JPS56105656A (en) 1981-08-22
JPS6041858B2 JPS6041858B2 (en) 1985-09-19

Family

ID=11695751

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55008532A Expired JPS6041858B2 (en) 1980-01-28 1980-01-28 semiconductor equipment

Country Status (1)

Country Link
JP (1) JPS6041858B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5967661A (en) * 1982-10-12 1984-04-17 Hitachi Ltd Semiconductor device
US4449504A (en) * 1982-03-31 1984-05-22 Nippondenso Co., Ltd. Distributor type fuel injection pump
US4910584A (en) * 1981-10-30 1990-03-20 Fujitsu Limited Semiconductor device
US5455385A (en) * 1993-06-28 1995-10-03 Harris Corporation Multilayer LTCC tub architecture for hermetically sealing semiconductor die, external electrical access for which is provided by way of sidewall recesses

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4910584A (en) * 1981-10-30 1990-03-20 Fujitsu Limited Semiconductor device
US4449504A (en) * 1982-03-31 1984-05-22 Nippondenso Co., Ltd. Distributor type fuel injection pump
JPS5967661A (en) * 1982-10-12 1984-04-17 Hitachi Ltd Semiconductor device
US5455385A (en) * 1993-06-28 1995-10-03 Harris Corporation Multilayer LTCC tub architecture for hermetically sealing semiconductor die, external electrical access for which is provided by way of sidewall recesses

Also Published As

Publication number Publication date
JPS6041858B2 (en) 1985-09-19

Similar Documents

Publication Publication Date Title
US4303934A (en) Molded lead frame dual in line package including a hybrid circuit
TW366575B (en) Semiconductor device and the manufacturing method
KR970067801A (en) Semiconductor device and manufacturing method thereof
KR950004467A (en) Semiconductor device and manufacturing method
JPH05283460A (en) Semiconductor device
US6184567B1 (en) Film capacitor and semiconductor package or device carrying same
JPS56105656A (en) Semiconductor device
JPH11243175A (en) Composite semiconductor device
JPS57166051A (en) Semiconductor device
JPH0317220B2 (en)
JPS6473753A (en) Semiconductor integrated circuit device
JP2691352B2 (en) Electronic component mounting device
JP2553665B2 (en) Semiconductor device
KR19980025890A (en) Multi-chip package with lead frame
JPH06216492A (en) Electronic device
KR19980044540A (en) Clip lead package
JPS57202747A (en) Electronic circuit device
KR100686823B1 (en) Semiconductor Package
JPS645895Y2 (en)
JPS6489356A (en) Hybrid integrated circuit
JPS647643A (en) Semiconductor device
JPH04324963A (en) Hybrid integrated circuit device
GB1504663A (en) Large area hybrid microcircuit assembly
JPH02271547A (en) Film carrier-type semiconductor device
JPS5735354A (en) Sealing method for semiconductor housing container