JPS6424838U - - Google Patents

Info

Publication number
JPS6424838U
JPS6424838U JP1987118406U JP11840687U JPS6424838U JP S6424838 U JPS6424838 U JP S6424838U JP 1987118406 U JP1987118406 U JP 1987118406U JP 11840687 U JP11840687 U JP 11840687U JP S6424838 U JPS6424838 U JP S6424838U
Authority
JP
Japan
Prior art keywords
substrate
lead portion
chip
circuit board
bonding wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1987118406U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987118406U priority Critical patent/JPS6424838U/ja
Publication of JPS6424838U publication Critical patent/JPS6424838U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/075Connecting or disconnecting of bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/015Manufacture or treatment of bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/015Manufacture or treatment of bond wires
    • H10W72/01515Forming coatings
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/541Dispositions of bond wires
    • H10W72/5445Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)

Description

【図面の簡単な説明】
図面は本考案の一実施例を示し、第1図は回路
基板の平面図で一部切欠部して示し、第2図は第
1図の2―2拡大断面図、第3図は樹脂液を適下
してICチツプとボンデイング用線とリード部の
外周面に被膜を形成する際の説明図であり、第4
図は従来の回路基板の中央縦断面図である。 尚、図中、基板……1、ICチツプ……3、導
線……4、リード部……4a、ボンデイング用線
……5、被膜……6とする。

Claims (1)

    【実用新案登録請求の範囲】
  1. 基板上に搭載されたICチツプと、基板上に配
    設された導線のリード部と、該チツプとリード部
    間とに渉つてループ状に接続されたボンデイング
    用線との夫々の外周面に沿つて、絶縁性樹脂から
    なる被膜を形成したことを特徴とする回路基板。
JP1987118406U 1987-07-31 1987-07-31 Pending JPS6424838U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987118406U JPS6424838U (ja) 1987-07-31 1987-07-31

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987118406U JPS6424838U (ja) 1987-07-31 1987-07-31

Publications (1)

Publication Number Publication Date
JPS6424838U true JPS6424838U (ja) 1989-02-10

Family

ID=31362738

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987118406U Pending JPS6424838U (ja) 1987-07-31 1987-07-31

Country Status (1)

Country Link
JP (1) JPS6424838U (ja)

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