JPS6431253A - Data transferring system - Google Patents

Abstract

PURPOSE:To shorten the occupying time of a bus by simultaneously outputting the address of data to be transferred and the reading signal of a memory to the memory in which the data to be transferred is stored and the address of a transfer destination and the writing signal of the memory to the memory of the data transfer destination. CONSTITUTION:An adder 15 adds the address inputted from an address bus 103 and a value inputted from a register 14 to generate the address of the data to be transferred in a RAM 17 and output to an address bus 104. Then, to the address bus of a local bus 102, the address of the address bus 104 is outputted and to the address bus of a system bus 102, the value of the address bus 103 is outputted. Then, at the time of making a memory read signal 105 and a memory write signal 106 active simultaneously, the memory read signal of the local bus side 102 side is made active to make the memory write signal of the system bus 101 side active and transfer the data in one cycle. Thereby, a time requiring for transferring the data is reduced and the occupying time of the bus is shortened.