JPS6431461A - Manufacture of bipolar transistor - Google Patents

Manufacture of bipolar transistor

Info

Publication number
JPS6431461A
JPS6431461A JP62188026A JP18802687A JPS6431461A JP S6431461 A JPS6431461 A JP S6431461A JP 62188026 A JP62188026 A JP 62188026A JP 18802687 A JP18802687 A JP 18802687A JP S6431461 A JPS6431461 A JP S6431461A
Authority
JP
Japan
Prior art keywords
region
impurity
base
layer
impurity region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62188026A
Other languages
Japanese (ja)
Inventor
Takayuki Gomi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP62188026A priority Critical patent/JPS6431461A/en
Publication of JPS6431461A publication Critical patent/JPS6431461A/en
Pending legal-status Critical Current

Links

Landscapes

  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To effectively connect a base active region to a base leading region (graft base region) while reducing (shallow junction) by forming second impurity region in contact with a first impurity region with the insulating layer of the sidewall of an impurity containing layer as a mask to be used as a connecting impurity region at the part of the low concentration first impurity region. CONSTITUTION:A sidewall 34 is formed as an insulating layer on the sidewall of a base leading electrode 26. Then, a thin polycrystalline silicon layer 35 is formed on a whole surface including an opening 28, and an impurity, such as B<+> or BF2<+> is implanted by ion implanting. Thereafter, it is annealed to diffuse a P-type impurity implanted to the layer 35 in the surface of an insular region 23, and a base active region 36 is formed as a second conductivity type (P-type) second impurity region by the P-type impurity diffused from the layer 35 in contact with a connecting low concentration impurity region 32. A base active region 36 formed by activating is connected through a connecting low concentration impurity region 32 to a graft base region 31, and further electrically connected to the electrode 26.
JP62188026A 1987-07-28 1987-07-28 Manufacture of bipolar transistor Pending JPS6431461A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62188026A JPS6431461A (en) 1987-07-28 1987-07-28 Manufacture of bipolar transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62188026A JPS6431461A (en) 1987-07-28 1987-07-28 Manufacture of bipolar transistor

Publications (1)

Publication Number Publication Date
JPS6431461A true JPS6431461A (en) 1989-02-01

Family

ID=16216362

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62188026A Pending JPS6431461A (en) 1987-07-28 1987-07-28 Manufacture of bipolar transistor

Country Status (1)

Country Link
JP (1) JPS6431461A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5010026A (en) * 1988-08-12 1991-04-23 Sony Corporation Process for making bipolar transistor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5010026A (en) * 1988-08-12 1991-04-23 Sony Corporation Process for making bipolar transistor

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