JPS6433962A - Linear image sensor - Google Patents

Linear image sensor

Info

Publication number
JPS6433962A
JPS6433962A JP62190683A JP19068387A JPS6433962A JP S6433962 A JPS6433962 A JP S6433962A JP 62190683 A JP62190683 A JP 62190683A JP 19068387 A JP19068387 A JP 19068387A JP S6433962 A JPS6433962 A JP S6433962A
Authority
JP
Japan
Prior art keywords
image sensor
linear image
semiconductor chip
patterns
defective
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62190683A
Other languages
Japanese (ja)
Inventor
Shigeto Maekawa
Hidenobu Ishikura
Satoshi Yamakawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP62190683A priority Critical patent/JPS6433962A/en
Publication of JPS6433962A publication Critical patent/JPS6433962A/en
Pending legal-status Critical Current

Links

Landscapes

  • Facsimile Heads (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)

Abstract

PURPOSE:To enable the number of non-defective obtained from one slice of semiconductor wafer to be increased compared with conventional one, by disposing at least two linear image sensor patterns in parallel on one semiconductor chip, thereby only one pattern of non-defective between them being used. CONSTITUTION:A strip of linear image sensor pattern 5 is formed on each of a plurality of semiconductor chips 6 into which one slice of semiconductor wafer is divided. In such a linear image sensor, at least two strips of linear image sensor patterns 5a, 5b are disposed in parallel on one semiconductor chip 6 so that only one pattern of non-defective between them is used. For example, two pairs of linear image sensor patterns 5a, 5b are formed on one semiconductor chip 6, with each of the patterns 5a, 5b being disposed symmetrically with respect to the central point of the semiconductor chip 6. And, if both the patterns 5a and 5b' are non-defective while both the patterns 5b and 5a' are defective, the other semiconductor chip 6' is caused to be so rotated in azimuth by 180 deg. as to be disposed in series with one semiconductor chip 6 with the two chips being met each other.
JP62190683A 1987-07-30 1987-07-30 Linear image sensor Pending JPS6433962A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62190683A JPS6433962A (en) 1987-07-30 1987-07-30 Linear image sensor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62190683A JPS6433962A (en) 1987-07-30 1987-07-30 Linear image sensor

Publications (1)

Publication Number Publication Date
JPS6433962A true JPS6433962A (en) 1989-02-03

Family

ID=16262141

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62190683A Pending JPS6433962A (en) 1987-07-30 1987-07-30 Linear image sensor

Country Status (1)

Country Link
JP (1) JPS6433962A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6803248B2 (en) 2001-12-21 2004-10-12 Freescale Semiconductor, Inc. Chemistry for etching quaternary interface layers on InGaAsP mostly formed between GaAs and InxGa(1-x)P layers

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6803248B2 (en) 2001-12-21 2004-10-12 Freescale Semiconductor, Inc. Chemistry for etching quaternary interface layers on InGaAsP mostly formed between GaAs and InxGa(1-x)P layers

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