JPS6445159A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6445159A JPS6445159A JP62200996A JP20099687A JPS6445159A JP S6445159 A JPS6445159 A JP S6445159A JP 62200996 A JP62200996 A JP 62200996A JP 20099687 A JP20099687 A JP 20099687A JP S6445159 A JPS6445159 A JP S6445159A
- Authority
- JP
- Japan
- Prior art keywords
- region
- surface region
- type isolated
- substrate body
- isolated layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
- H10D12/411—Insulated-gate bipolar transistors [IGBT]
- H10D12/441—Vertical IGBTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/40—Crystalline structures
Landscapes
- Bipolar Transistors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
PURPOSE:To provide a conductivity-modulated MOSFET with high breakdown strength by a method wherein an island region isolated from a base region by a first conductivity type isolated layer and a first conductivity type isolated and diffused region formed on a surface region to reach the isolated layer is provided. CONSTITUTION:A first n<->surface region 3 as a first substrate body is formed on a p<+>region 1 while a p-type isolated layer 5 as a second substrate body is formed in a specified position on the main substrate to be a second n<->surface region 4. Next, the first substrate body and the second substrate body are junctioned by direct junction of respective substrates into an n<->surface region 2 in specified thickness simultaneously forming the p-type isolated layer 5 in specified position on the boundary part between the first n<->surface region 3 and the second n<->surface region 4. Then, the second n<->surface region 4 is divided into a surface region 4a for base region and an island region 4b wherein other semiconductor elements 20, 30 are formed by the p-type isolated layer 5 and a p-type isolated and diffused region 6. Through these procedures, a semiconductor device can be provided with high breakdown strength.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62200996A JPS6445159A (en) | 1987-08-13 | 1987-08-13 | Semiconductor device |
| US07/213,073 US4881107A (en) | 1987-07-03 | 1988-06-29 | IC device having a vertical MOSFET and an auxiliary component |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62200996A JPS6445159A (en) | 1987-08-13 | 1987-08-13 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6445159A true JPS6445159A (en) | 1989-02-17 |
Family
ID=16433772
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62200996A Pending JPS6445159A (en) | 1987-07-03 | 1987-08-13 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6445159A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0683529A1 (en) * | 1994-05-19 | 1995-11-22 | Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno - CoRiMMe | Power integrated circuit ("PIC") structure with a vertical IGBT, and manufacturing process thereof |
| JPH07321214A (en) * | 1994-05-19 | 1995-12-08 | Consorzio Per La Ric Sulla Microelettronica Nel Mezzogiorno | Power integrated circuit structure and manufacturing method thereof |
| WO2012020498A1 (en) * | 2010-08-12 | 2012-02-16 | 富士電機株式会社 | Manufacturing method for semi-conductor device |
-
1987
- 1987-08-13 JP JP62200996A patent/JPS6445159A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0683529A1 (en) * | 1994-05-19 | 1995-11-22 | Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno - CoRiMMe | Power integrated circuit ("PIC") structure with a vertical IGBT, and manufacturing process thereof |
| JPH07321214A (en) * | 1994-05-19 | 1995-12-08 | Consorzio Per La Ric Sulla Microelettronica Nel Mezzogiorno | Power integrated circuit structure and manufacturing method thereof |
| US5556792A (en) * | 1994-05-19 | 1996-09-17 | Consorzio Per La Ricerca Sulla Microelecttronica Nel Mezzogiorno | Process for manufacturing a power integrated circuit ("PIC") structure with a vertical IGBT |
| US5703385A (en) * | 1994-05-19 | 1997-12-30 | Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno | Power integrated circuit ("PIC") structure with a vertical IGBT |
| WO2012020498A1 (en) * | 2010-08-12 | 2012-02-16 | 富士電機株式会社 | Manufacturing method for semi-conductor device |
| US8685801B2 (en) | 2010-08-12 | 2014-04-01 | Fuji Electric Co., Ltd. | Method of manufacturing semiconductor device |
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