JPS6464257A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6464257A
JPS6464257A JP62104727A JP10472787A JPS6464257A JP S6464257 A JPS6464257 A JP S6464257A JP 62104727 A JP62104727 A JP 62104727A JP 10472787 A JP10472787 A JP 10472787A JP S6464257 A JPS6464257 A JP S6464257A
Authority
JP
Japan
Prior art keywords
regions
base width
base region
base
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62104727A
Other languages
Japanese (ja)
Inventor
Shinichi Shiyugiyou
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62104727A priority Critical patent/JPS6464257A/en
Publication of JPS6464257A publication Critical patent/JPS6464257A/en
Pending legal-status Critical Current

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  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To realize a bipolar transistor having both high current amplification factor and high collector dielectric strength, by providing a base region so that it includes regions with a smaller base width and regions with a larger base width arranged altenately and periodically with a certain space. CONSTITUTION:A base region 2 having a dopant thickness, i.e. base width identical to those of prior arts is formed, while in this base region 2 regions 3 having a larger base width are provided periodically with a proper space from each other. These larger base width regions 3 may be formed, after formation of the base region 2, by introducing a dopant deep in regions as desired by means of a selective dopant introducing technique such as ion implantation or the like. In this manner, diffusion of a depletion layer 5 into a collector region 4 can be accelerated with the diffusion of the depletion layer 6 into the base region 2 inhibited. Accordingly, a high current amplification factor can be obtained in the base region 2 having a smaller base width, while high collector dielectric strength can be obtained in the larger base width regions 3. As a result, a bipolar transistor having high current amplification factor together with high collector dielectric strength can be obtained.
JP62104727A 1987-04-30 1987-04-30 Semiconductor device Pending JPS6464257A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62104727A JPS6464257A (en) 1987-04-30 1987-04-30 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62104727A JPS6464257A (en) 1987-04-30 1987-04-30 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6464257A true JPS6464257A (en) 1989-03-10

Family

ID=14388528

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62104727A Pending JPS6464257A (en) 1987-04-30 1987-04-30 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6464257A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9461152B2 (en) 2015-02-16 2016-10-04 Toyota Jidosha Kabushiki Kaisha Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9461152B2 (en) 2015-02-16 2016-10-04 Toyota Jidosha Kabushiki Kaisha Semiconductor device

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