JPS646566B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a highly accurate semiconductor device in which a timer circuit that generates a clock of an arbitrary frequency is constructed using an integrated circuit.

FIG. 1 is a circuit diagram showing a conventional timer circuit semiconductor device. In the figure, 1 is a clock terminal to which the clock φcp shown in FIG _. , 4 is a power supply terminal to which the power supply voltage Vcc is applied, 5
is a MOS transistor whose drain and gate are connected to node 3 and whose source is connected to ground, 6
is a MOS transistor whose drain is connected to node 7, whose gate is connected to ground, and whose source is connected to node 3; 8 is a capacitor with a capacitance C _ST whose one end is connected to node 7 and the other end is connected to ground; 9 is a stray capacitance of capacitance C ₁ at node 3, 10 has its drain connected to node 11, and its gate connected to node 7
12 is a load transistor of node 11, and 13 is an input terminal 13a and an output terminal 13b.
14 has a trigger circuit whose input terminal 13a is connected to the node 11, whose drain is connected to the power supply terminal 4 and whose gate is connected to the output terminal 13 of the trigger circuit 13.
MOS connected to b and source connected to node 7
It is a transistor.

Note that FIG. 2b shows the voltage waveform at node 3, and FIG. 2c shows the voltage waveform at node 7.

Next, the operation of the semiconductor device having the above configuration will be explained with reference to FIGS. 2a to 2c. First, the node 7 is charged in advance to the power supply voltage Vc.c. through the MOS transistor 14. Then time
At _t1 , when the clock φcp goes from the "L" level to the "H" level, the capacitive coupling by the capacitor 2 causes the node 3 to go to the "H" level. Therefore, the MOS transistor 5 turns on (the MOS transistor 6 remains off), and the charge at the node 3 is discharged through the on-state MOS transistor 5, so this node When the level of MOS transistor 3 starts to fall and becomes equal to V _TH (the threshold voltage of the transistor), that is, at time t ₂ , the MOS transistor 5 turns off,
The discharge stops. Next, at time _t3 , when the clock φcp goes from the "H" level to the "L" level as shown in FIG. , drops to a negative potential. Therefore, the MOS transistor 6 is turned on (the MOS transistor 5 remains off). Therefore, the positive charge accumulated in the capacitor 8 is transferred to the node 7 and the MOS transistor 6 in the on state.
is transferred to node 3 via. And node 3
When the level approaches 0V and becomes equal to the _-VTH level, MOS transistor 6 is turned off and the movement of charge from capacitor 8 to node 3 is stopped. Then, when node 7 drops to the threshold voltage V _TH as shown in Figure 2c, the MOS
Transistor 10 is turned off. This MOS
Due to the off state of the transistor 10, the trigger circuit 13 enters the operating state, so that its output terminal 13b
An output of "H" level is sent from. For this reason,
MOS transistor 14 is turned on. Therefore, node 7 returns to the original "H" level. After that, the trigger circuit 13 becomes inactive, the MOS transistor 14 becomes off,
Node 7 becomes “H” floating. below,
It works repeatedly. Next, in the above operation, the amount of charge Q _T transferred from the capacitor 8 to the capacitor 2 per cycle of the clock φcp is ideally expressed by equation (1).

Q _T = C _T (Vcc−2V _TH ) ……(1) However, in reality, there is a loss α, and the effective
It is shown by equation (2).

Q _T =C _T (Vcc−2V _TH −α) ……(2) Here, α is (i) There is always a stray capacitance C ₁ at node 3.
This reduces the capacitive coupling effect of the capacitor 2. (ii) Since the conductance of MOS transistors 5 and 6 is finite, it takes an infinite amount of time for the level of node 3 to reach ±V _TH .

Next, using equation (2) above, the potential change ΔV per cycle of clock φcp at node 7 can be found as shown in equation (3).

ΔV=1/C _ST・Q _T =C _T /C _ST (Vcc−2V _TH −α) ……(3) The feature of this timer is that the amount of charge Q _T transferred per cycle is independent of the level of node 7. is always constant. Therefore, the timer set time _tset is equal to the time it takes for node 7 to fall from Vcc to _VTH , and can be expressed by equation (4).

t _set = 1/f _cp・Vcc−V _TH /ΔV =1/f _cp (C _ST /C _T )・Vcc−V _TH /Vcc−2V _TH− 〓…
...(4) Here, _cp is the frequency of clock φcp. From this equation (4), t _set is a function of the oscillation frequency of the clock φcp, the ratio of C _ST /C _T , the V _TH of the MOS transistor, and the power supply voltage. Thereby, by setting the capacitance _CT of the capacitor 2 and the capacitance _CST of the capacitor 8 to appropriate values, a timer having an arbitrary period can be realized.

However, in the semiconductor device that constitutes the conventional timer circuit, after starting the timer operation,
When the level of the power supply voltage Vcc decreases for some reason and the "H" level of the clock φcp from the IC internal oscillator to which the power supply voltage Vcc is supplied decreases, it moves per cycle. The amount of charge decreases and the set time
The disadvantage is that t _set is long.

Therefore, the object of this invention is _{to set} the set time t set
An object of the present invention is to provide a semiconductor device that can suppress fluctuations in time and configure a highly accurate timer circuit.

In order to achieve such an object, the present invention provides a clamp transistor whose drain is connected to the power supply terminal and whose gate and source are connected to the second node, and will be described in detail below using examples. do.

FIG. 3 is a circuit diagram showing an embodiment of a semiconductor device according to the present invention. In the figure, 15 is a clamp transistor whose drain is connected to the power supply terminal 4 and whose gate and source are connected to the node 7.

Next, the operation of the semiconductor device according to the above configuration will be explained, but it goes without saying that the operation is the same as that shown in FIG. 1 when there is no level fluctuation of the power supply voltage Vcc.

Next, after the timer starts operating, for some reason the level of the power supply voltage Vcc drops to ΔV _D
When the voltage decreases by (>V _TH ), the clamp transistor 15 is turned on, and the level of the node 7 is clamped to (V _DD −ΔV _D )+V _TH . For this reason,
The set time t _set2 can be expressed by equation (5).

t _set2 = 1/f _cp (C _ST /C _T ) ・[(Vcc−ΔV _D )+V _TH ]−V _TH /(Vcc−ΔV _D )−
2V _TH- (5) In FIG. 1, when the level of the power supply voltage Vcc decreases by ΔV _D (>V _TH ), the set time can be expressed by equation (6).

t _set1 = 1/f _cp (C _ST /C _T ) ・Vcc−V _TH /(Vcc−∆V _D )−2V _TH− 〓 ……(6) However, the fluctuation of the frequency cp of the clock φcp can be ignored. shall be.

Therefore, the set time in the circuit of Figure 1
The variation ratio Δt _set1 of t _set1 can be expressed by equation (7).

Δt _set1 = t _set1 / t _set = 1/(1-ΔV _D /Vcc-2V _TH- 〓) ...(7) On the other hand, the variation ratio Δt _set2 of the set time t _set2 in Fig. 3 is expressed by equation (8). can be shown.

Δt _set2 = t _set2 / t _set = (1−ΔV _D −V _TH /Vcc−V _TH
) /(1-ΔV _D /Vcc-2V _TH- 〓) ...(8) Next, the set time variation ratio Δt _set1 in Fig. 1 and the set time variation ratio Δt _set2 in Fig. 3
_{Comparing the magnitude of _ _ _} Since fluctuations in the set time can be reduced, accuracy can be increased accordingly.

In the above embodiment, the case where the threshold voltage V _TH of the clamp transistor 15 is the same as that of other MOS transistors has been explained, but if this threshold voltage V _TH is smaller than the other MOS transistors, the set time variation ratio Δt _set2 Of course, it becomes even smaller.

As described above in detail, the semiconductor device according to the present invention has the advantage that a timer circuit that generates an arbitrary frequency can be constructed with high precision using an integrated circuit.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing a conventional timer circuit semiconductor device, Figures 2a, 2b, and 2c.
1 is a diagram showing waveforms of various parts in FIG. 1, and FIG. 3 is a circuit diagram showing an embodiment of a semiconductor device according to the present invention. 1...Clock terminal, 2...Capacitor, 3...
...Node, 4...Power terminal, 5 and 6...
MOS transistor, 7... Node, 8... Capacitor, 9... Stray capacitance, 10... MOS transistor, 11... Node, 12... Load transistor, 13... Trigger circuit, 14... MOS transistor, 15... ...Clamp transistor. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1. In a semiconductor device that has at least an internal oscillator for generating a clock signal and a timer whose operation is controlled by supplying the clock signal to an input terminal, and a common power supply voltage is supplied to them, one end is connected to the clock signal. a first capacitor connected to the input terminal of the signal and having its other end connected to a first node; and a first MOS transistor having its drain and gate connected to this first node and its source connected to ground. and a second MOS transistor having a source connected to the first node, a drain connected to the second node, and a gate connected to ground, and one end connected to the second node,
a second capacitor whose other end is connected to ground;
a third MOS transistor having a drain connected to a power supply terminal, a gate connected to a terminal to which a trigger signal is applied, and a source connected to a second node;
a fourth MOS transistor whose drain is connected to the load transistor, whose gate is connected to the second node, and whose source is connected to ground; and whose input terminal is connected to the drain of the fourth MOS transistor and outputs a trigger signal. and a clamp transistor having a drain connected to a power supply terminal and a gate and a source connected to the second node.