JPS647621A - Manufacture of mesfet - Google Patents

Manufacture of mesfet

Info

Publication number
JPS647621A
JPS647621A JP16338587A JP16338587A JPS647621A JP S647621 A JPS647621 A JP S647621A JP 16338587 A JP16338587 A JP 16338587A JP 16338587 A JP16338587 A JP 16338587A JP S647621 A JPS647621 A JP S647621A
Authority
JP
Japan
Prior art keywords
layer
gate electrode
shape
mask
desired gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16338587A
Other languages
Japanese (ja)
Inventor
Takeshi Yagihara
Akira Miura
Hirofumi Matsuda
Shinji Kobayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yokogawa Electric Corp
Original Assignee
Yokogawa Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yokogawa Electric Corp filed Critical Yokogawa Electric Corp
Priority to JP16338587A priority Critical patent/JPS647621A/en
Publication of JPS647621A publication Critical patent/JPS647621A/en
Pending legal-status Critical Current

Links

Landscapes

  • Drying Of Semiconductors (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To form a fine gate electrode and to obtain a high integration by laminating a W gate electrode layer, a Ni layer, an Si3N4 layer and a resist layer on a semiconductor substrate, and sequentially forming the layers by a specific etching method into the shape of a desired gate electrode. CONSTITUTION:A W gate electrode layer 6, an Ni layer 8, an Si3N4 layer 9 and a resist layer 10 are sequentially laminated on a semiconductor substrate 5, and with the layer 10 as a mask the layer 9 is formed by a plasma etching in the shape of a desired gate electrode. Then, with the layer 9 as a mask the layer 8 is formed by argon ion milling into the shape of a desired gate electrode, with the layer 8 as a mask the layer 6 is formed by fluorine radical beam etching into the shape of a desired gate electrode. For example, as the layer 6 1000Angstrom of TaWSi layer 6a is formed, and approx. 1500Angstrom of a W layer 6b is further formed. After the layer 7 is formed 600Angstrom thereon, the layer 8 is formed approx. 600Angstrom .
JP16338587A 1987-06-30 1987-06-30 Manufacture of mesfet Pending JPS647621A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16338587A JPS647621A (en) 1987-06-30 1987-06-30 Manufacture of mesfet

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16338587A JPS647621A (en) 1987-06-30 1987-06-30 Manufacture of mesfet

Publications (1)

Publication Number Publication Date
JPS647621A true JPS647621A (en) 1989-01-11

Family

ID=15772883

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16338587A Pending JPS647621A (en) 1987-06-30 1987-06-30 Manufacture of mesfet

Country Status (1)

Country Link
JP (1) JPS647621A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06291089A (en) * 1991-10-28 1994-10-18 American Teleph & Telegr Co <Att> Method for forming patterned tungsten layer
JPH08186120A (en) * 1994-12-28 1996-07-16 Nec Corp Manufacture of semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06291089A (en) * 1991-10-28 1994-10-18 American Teleph & Telegr Co <Att> Method for forming patterned tungsten layer
JPH08186120A (en) * 1994-12-28 1996-07-16 Nec Corp Manufacture of semiconductor device

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