JPS64770A - Compound semiconductor integrated circuit - Google Patents

Compound semiconductor integrated circuit

Info

Publication number
JPS64770A
JPS64770A JP62064015A JP6401587A JPS64770A JP S64770 A JPS64770 A JP S64770A JP 62064015 A JP62064015 A JP 62064015A JP 6401587 A JP6401587 A JP 6401587A JP S64770 A JPS64770 A JP S64770A
Authority
JP
Japan
Prior art keywords
fet
film
compound semiconductor
deposited
rear surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62064015A
Other languages
Japanese (ja)
Other versions
JPH01770A (en
Inventor
Mikio Kanamori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP62064015A priority Critical patent/JPS64770A/en
Publication of JPH01770A publication Critical patent/JPH01770A/en
Publication of JPS64770A publication Critical patent/JPS64770A/en
Pending legal-status Critical Current

Links

Landscapes

  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE: To form each FET having one kind of an operating layer and to simplify the manufacturing process to a large extent, by arranging the gate electrodes of the field effect transistors in the different orientations in accordance with the magnitudes of threshold voltage values to be controlled, and providing an insulating film or a metal film having stress on the rear surface of a compound semiconductor substrate having the transistors.
CONSTITUTION: Tungsten silicide is deposited on an semi-insulating substrate 5 so as to cover an operating layer 3 to a thickness of 0.5μm by using a sputtering method. Thereafter, the WSi film is patterned into a specified pattern. Thus a Schottky gate 1 is formed. Then, Si ions are implanted. Annealing is performed in an As pressure atmosphere at 750°C for 20 minutes. Thus n+ layers 4a and 4b are formed. A source electrode 2a and a drain electrode 2b comprising metal layers of AuGe-Ni are formed. Finally a W film 6 having a film stress of 2×1010dyn/cm2 is deposited on the entire rear surface of the GaAs substrate to a thickness of 4μm by a sputtering method. An enhancement type FET is obtained from a [011] FET, and a depletion type FET is obtained from a [011] FET.
COPYRIGHT: (C)1989,JPO&Japio
JP62064015A 1987-03-20 1987-03-20 Compound semiconductor integrated circuit Pending JPS64770A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62064015A JPS64770A (en) 1987-03-20 1987-03-20 Compound semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62064015A JPS64770A (en) 1987-03-20 1987-03-20 Compound semiconductor integrated circuit

Publications (2)

Publication Number Publication Date
JPH01770A JPH01770A (en) 1989-01-05
JPS64770A true JPS64770A (en) 1989-01-05

Family

ID=13245920

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62064015A Pending JPS64770A (en) 1987-03-20 1987-03-20 Compound semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS64770A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01273359A (en) * 1988-04-26 1989-11-01 Nec Corp Semiconductor integrated circuit
US6278141B1 (en) 1998-07-21 2001-08-21 Fujitsu Limited Enhancement-mode semiconductor device

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58145168A (en) * 1982-02-24 1983-08-29 Fujitsu Ltd Semiconductor device
JPS5923566A (en) * 1982-07-30 1984-02-07 Hitachi Ltd Gallium arsenide semiconductor device
JPS5979577A (en) * 1982-10-29 1984-05-08 Fujitsu Ltd Semiconductor integrated circuit device
JPS60176276A (en) * 1984-02-22 1985-09-10 Nec Corp Gallium arsenide integrated circuit
JPS61115347A (en) * 1984-11-10 1986-06-02 Fujitsu Ltd Complementary type field-effect semiconductor device
JPS61129878A (en) * 1984-11-29 1986-06-17 Fujitsu Ltd Semiconductor device
JPS61268070A (en) * 1984-11-29 1986-11-27 Fujitsu Ltd Semiconductor device

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58145168A (en) * 1982-02-24 1983-08-29 Fujitsu Ltd Semiconductor device
JPS5923566A (en) * 1982-07-30 1984-02-07 Hitachi Ltd Gallium arsenide semiconductor device
JPS5979577A (en) * 1982-10-29 1984-05-08 Fujitsu Ltd Semiconductor integrated circuit device
JPS60176276A (en) * 1984-02-22 1985-09-10 Nec Corp Gallium arsenide integrated circuit
JPS61115347A (en) * 1984-11-10 1986-06-02 Fujitsu Ltd Complementary type field-effect semiconductor device
JPS61129878A (en) * 1984-11-29 1986-06-17 Fujitsu Ltd Semiconductor device
JPS61268070A (en) * 1984-11-29 1986-11-27 Fujitsu Ltd Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01273359A (en) * 1988-04-26 1989-11-01 Nec Corp Semiconductor integrated circuit
US6278141B1 (en) 1998-07-21 2001-08-21 Fujitsu Limited Enhancement-mode semiconductor device

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