JPS6477157A - Insulated-gate field-effect semiconductor device - Google Patents

Insulated-gate field-effect semiconductor device

Info

Publication number
JPS6477157A
JPS6477157A JP62234525A JP23452587A JPS6477157A JP S6477157 A JPS6477157 A JP S6477157A JP 62234525 A JP62234525 A JP 62234525A JP 23452587 A JP23452587 A JP 23452587A JP S6477157 A JPS6477157 A JP S6477157A
Authority
JP
Japan
Prior art keywords
source region
type
regions
insulated
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62234525A
Other languages
Japanese (ja)
Other versions
JP2601664B2 (en
Inventor
Takayuki Nibuya
Yoshihiro Ogata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Japan Ltd
Original Assignee
Texas Instruments Japan Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Japan Ltd filed Critical Texas Instruments Japan Ltd
Priority to JP62234525A priority Critical patent/JP2601664B2/en
Publication of JPS6477157A publication Critical patent/JPS6477157A/en
Application granted granted Critical
Publication of JP2601664B2 publication Critical patent/JP2601664B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To make a semiconductor region to absorb hot carriers generated while a device is in operation so as to prevent latch-up of the device by a method wherein the opposite conductivity type semiconductor region mentioned above is provided in a source region so as to be contacted with lower layer of the source region. CONSTITUTION:Plural N<+>-type semiconductor regions 30 are formed like islands in a common P<+>-type source region 3 of P channel MOSFETs 2a and 2b provided in an N-type well 7, and the regions 30 are contacted with the N-type well 7 under them. Therefore, hot electrons e generated while the MOSFETs 2a and 2b are in operation can be absorbed into the N<+>-type regions 30 as shown by arrows. In result, a local potential drop just under the source region can be prevented, so that a upright PNP parasitic bipolar transistor 13 can be prevented from being on due to a forward bias.
JP62234525A 1987-09-18 1987-09-18 Insulated gate field effect semiconductor device Expired - Fee Related JP2601664B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62234525A JP2601664B2 (en) 1987-09-18 1987-09-18 Insulated gate field effect semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62234525A JP2601664B2 (en) 1987-09-18 1987-09-18 Insulated gate field effect semiconductor device

Publications (2)

Publication Number Publication Date
JPS6477157A true JPS6477157A (en) 1989-03-23
JP2601664B2 JP2601664B2 (en) 1997-04-16

Family

ID=16972393

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62234525A Expired - Fee Related JP2601664B2 (en) 1987-09-18 1987-09-18 Insulated gate field effect semiconductor device

Country Status (1)

Country Link
JP (1) JP2601664B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7545005B2 (en) 2003-03-27 2009-06-09 Mitsubishi Denki Kabushiki Kaisha Semiconductor device capable of avoiding latchup breakdown resulting from negative variation of floating offset voltage
JP2009231851A (en) * 2009-07-09 2009-10-08 Mitsubishi Electric Corp Semiconductor device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60253262A (en) * 1984-05-29 1985-12-13 Nec Corp Mos integrated circuit device
JPS61156882A (en) * 1984-12-28 1986-07-16 Toshiba Corp Double-diffused igfet and manufacture thereof
JPS62200757A (en) * 1986-02-28 1987-09-04 Toshiba Corp Mos-type semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60253262A (en) * 1984-05-29 1985-12-13 Nec Corp Mos integrated circuit device
JPS61156882A (en) * 1984-12-28 1986-07-16 Toshiba Corp Double-diffused igfet and manufacture thereof
JPS62200757A (en) * 1986-02-28 1987-09-04 Toshiba Corp Mos-type semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7545005B2 (en) 2003-03-27 2009-06-09 Mitsubishi Denki Kabushiki Kaisha Semiconductor device capable of avoiding latchup breakdown resulting from negative variation of floating offset voltage
US7777279B2 (en) 2003-03-27 2010-08-17 Mitsubishi Denki Kabushiki Kaisha Semiconductor device capable of avoiding latchup breakdown resulting from negative variation of floating offset voltage
JP2009231851A (en) * 2009-07-09 2009-10-08 Mitsubishi Electric Corp Semiconductor device

Also Published As

Publication number Publication date
JP2601664B2 (en) 1997-04-16

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