JPS6480031A - Manufacture of resin sealed semiconductor device - Google Patents

Manufacture of resin sealed semiconductor device

Info

Publication number
JPS6480031A
JPS6480031A JP23790487A JP23790487A JPS6480031A JP S6480031 A JPS6480031 A JP S6480031A JP 23790487 A JP23790487 A JP 23790487A JP 23790487 A JP23790487 A JP 23790487A JP S6480031 A JPS6480031 A JP S6480031A
Authority
JP
Japan
Prior art keywords
semiconductor chip
lead frame
sucking hole
vacuum
manufacture
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23790487A
Other languages
English (en)
Inventor
Kazuo Usada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP23790487A priority Critical patent/JPS6480031A/ja
Publication of JPS6480031A publication Critical patent/JPS6480031A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
JP23790487A 1987-09-21 1987-09-21 Manufacture of resin sealed semiconductor device Pending JPS6480031A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23790487A JPS6480031A (en) 1987-09-21 1987-09-21 Manufacture of resin sealed semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23790487A JPS6480031A (en) 1987-09-21 1987-09-21 Manufacture of resin sealed semiconductor device

Publications (1)

Publication Number Publication Date
JPS6480031A true JPS6480031A (en) 1989-03-24

Family

ID=17022155

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23790487A Pending JPS6480031A (en) 1987-09-21 1987-09-21 Manufacture of resin sealed semiconductor device

Country Status (1)

Country Link
JP (1) JPS6480031A (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6710464B2 (en) 2001-09-10 2004-03-23 Renesas Technology Corp. Resin mold semiconductor device
US6716667B2 (en) 2001-09-05 2004-04-06 Renesas Technology Corp. Semiconductor device manufacturing method, making negative pressure for fixing a chip on a substrate

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6716667B2 (en) 2001-09-05 2004-04-06 Renesas Technology Corp. Semiconductor device manufacturing method, making negative pressure for fixing a chip on a substrate
US6710464B2 (en) 2001-09-10 2004-03-23 Renesas Technology Corp. Resin mold semiconductor device

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