JPS6484349A - Multi-port memory - Google Patents

Multi-port memory

Info

Publication number
JPS6484349A
JPS6484349A JP62242186A JP24218687A JPS6484349A JP S6484349 A JPS6484349 A JP S6484349A JP 62242186 A JP62242186 A JP 62242186A JP 24218687 A JP24218687 A JP 24218687A JP S6484349 A JPS6484349 A JP S6484349A
Authority
JP
Japan
Prior art keywords
access
access ports
data
memories
phase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62242186A
Other languages
Japanese (ja)
Other versions
JPH0477934B2 (en
Inventor
Shinichi Habata
Yuzuru Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62242186A priority Critical patent/JPS6484349A/en
Publication of JPS6484349A publication Critical patent/JPS6484349A/en
Publication of JPH0477934B2 publication Critical patent/JPH0477934B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Dram (AREA)

Abstract

PURPOSE:To process shared memory access in parallel by providing the titled memory with plural access ports so that plural data can be simultaneously read out and written. CONSTITUTION:Memories 11-14, 21-24, 31n34, 41-44 corresponding to the square of the number of access ports 0-3 arranged like a grating are used and an access cycle is divided into a reading phase and a writing phase. In the reading phase, respective access ports use the memories belonging to specific columns, and also in the writing phase, respective access ports 0-3 similarly use the memories belonging to the specific rows. When the total number of data to be access is the number of access ports 0-3, or below the optional number of data can be read out and written within one access cycle.
JP62242186A 1987-09-25 1987-09-25 Multi-port memory Granted JPS6484349A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62242186A JPS6484349A (en) 1987-09-25 1987-09-25 Multi-port memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62242186A JPS6484349A (en) 1987-09-25 1987-09-25 Multi-port memory

Publications (2)

Publication Number Publication Date
JPS6484349A true JPS6484349A (en) 1989-03-29
JPH0477934B2 JPH0477934B2 (en) 1992-12-09

Family

ID=17085585

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62242186A Granted JPS6484349A (en) 1987-09-25 1987-09-25 Multi-port memory

Country Status (1)

Country Link
JP (1) JPS6484349A (en)

Also Published As

Publication number Publication date
JPH0477934B2 (en) 1992-12-09

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