JPS6484490A - Multi-port memory - Google Patents

Multi-port memory

Info

Publication number
JPS6484490A
JPS6484490A JP62242188A JP24218887A JPS6484490A JP S6484490 A JPS6484490 A JP S6484490A JP 62242188 A JP62242188 A JP 62242188A JP 24218887 A JP24218887 A JP 24218887A JP S6484490 A JPS6484490 A JP S6484490A
Authority
JP
Japan
Prior art keywords
data
memory
memories
bit
access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62242188A
Other languages
Japanese (ja)
Other versions
JPH0548559B2 (en
Inventor
Shinichi Habata
Yuzuru Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62242188A priority Critical patent/JPS6484490A/en
Publication of JPS6484490A publication Critical patent/JPS6484490A/en
Publication of JPH0548559B2 publication Critical patent/JPH0548559B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Static Random-Access Memory (AREA)

Abstract

PURPOSE:To simultaneously parallel-processing a sharing memory access by being equipped with plural access ports arranged in a lattice-shaped way, and reading and writing plural data at the same time. CONSTITUTION:For a memory part to store the data of multi-port memory 100 with one-bit width, 16 memories 130 with one-bit width are arranged in the lattice-shape way at 4 rows and 4 columns. By preparing the refreshening function of a dynamic memory, the dynamic memory at one mega bit can be used, and the memory with large capacity can be realized. Further, decoders 110 used for the reading of the data bit are prepared at the respective columns of the memories, and decoders 120 used for the writing of the data are prepared at the respective rows of the memories. Thus, by constituting as the above, the arbitrary number of the data can be read and written during one access cycle when the number of the data is <=the number of access ports.
JP62242188A 1987-09-25 1987-09-25 Multi-port memory Granted JPS6484490A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62242188A JPS6484490A (en) 1987-09-25 1987-09-25 Multi-port memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62242188A JPS6484490A (en) 1987-09-25 1987-09-25 Multi-port memory

Publications (2)

Publication Number Publication Date
JPS6484490A true JPS6484490A (en) 1989-03-29
JPH0548559B2 JPH0548559B2 (en) 1993-07-21

Family

ID=17085612

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62242188A Granted JPS6484490A (en) 1987-09-25 1987-09-25 Multi-port memory

Country Status (1)

Country Link
JP (1) JPS6484490A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007141999A1 (en) 2006-06-02 2007-12-13 Renesas Technology Corp. Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007141999A1 (en) 2006-06-02 2007-12-13 Renesas Technology Corp. Semiconductor device

Also Published As

Publication number Publication date
JPH0548559B2 (en) 1993-07-21

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees