JPS6486230A - Analog/digital converter - Google Patents

Analog/digital converter

Info

Publication number
JPS6486230A
JPS6486230A JP24319287A JP24319287A JPS6486230A JP S6486230 A JPS6486230 A JP S6486230A JP 24319287 A JP24319287 A JP 24319287A JP 24319287 A JP24319287 A JP 24319287A JP S6486230 A JPS6486230 A JP S6486230A
Authority
JP
Japan
Prior art keywords
trigger
data
memory
signal
trigger signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24319287A
Other languages
Japanese (ja)
Inventor
Masatoshi Sugimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Facom Corp
Original Assignee
Fuji Facom Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Facom Corp filed Critical Fuji Facom Corp
Priority to JP24319287A priority Critical patent/JPS6486230A/en
Publication of JPS6486230A publication Critical patent/JPS6486230A/en
Pending legal-status Critical Current

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  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE:To detect a correct trigger timing by providing a means to input directly a trigger signal as trigger data and holding the trigger data to a memory together with the converting data. CONSTITUTION:When a trigger signal (a) is inputted, for a trigger signal (f) obtained through a filter 1, the timing is later than the trigger signal (a). Since for trigger data a' through a receiver 5, the delay is not generated to the trigger signal (a), '1' and AD converting data (d) as the trigger data a' are written into a memory 4. Thus, at the time of collecting the data, the trigger signal (a) is sampled for a constant period together with an analog signal (b) and inputted and held into the memory 4 as the trigger data a' and the AD converting data (d). After the data are collected, the correct trigger timing can be detected by reading the trigger data a' of the memory 4.
JP24319287A 1987-09-28 1987-09-28 Analog/digital converter Pending JPS6486230A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24319287A JPS6486230A (en) 1987-09-28 1987-09-28 Analog/digital converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24319287A JPS6486230A (en) 1987-09-28 1987-09-28 Analog/digital converter

Publications (1)

Publication Number Publication Date
JPS6486230A true JPS6486230A (en) 1989-03-30

Family

ID=17100200

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24319287A Pending JPS6486230A (en) 1987-09-28 1987-09-28 Analog/digital converter

Country Status (1)

Country Link
JP (1) JPS6486230A (en)

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