JPS648662A - Supplementary semiconductor device - Google Patents

Supplementary semiconductor device

Info

Publication number
JPS648662A
JPS648662A JP62164328A JP16432887A JPS648662A JP S648662 A JPS648662 A JP S648662A JP 62164328 A JP62164328 A JP 62164328A JP 16432887 A JP16432887 A JP 16432887A JP S648662 A JPS648662 A JP S648662A
Authority
JP
Japan
Prior art keywords
transistor
insulating film
vertical type
channel transistor
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62164328A
Other languages
Japanese (ja)
Inventor
Hiroyuki Morita
Shuichi Oda
Yasuaki Inoue
Kiyoteru Kobayashi
Kiichi Nishikawa
Tadashi Nishimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP62164328A priority Critical patent/JPS648662A/en
Publication of JPS648662A publication Critical patent/JPS648662A/en
Pending legal-status Critical Current

Links

Landscapes

  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To obtain a semiconductor device which is strong against a latchup phenomenon and a software error, and has a high integration and high reliability by forming only an active region in a vertical type on an insulating film when a MOS transistor is formed on an interlayer insulating film and utilizing the whole side face as a transistor. CONSTITUTION:A single crystalline layer is formed in a vertical type on an interlayer insulating film 1, an impurity is doped as active regions 4, 5, 6, and a P-channel transistor 2 and an N-channel transistor 3 are composed. In this MOS transistor, the N-channel transistor and the P-channel transistor are completely isolated. Further, since the active region is formed in the vertical type, a transistor having a large channel width even in a small area can be formed.
JP62164328A 1987-06-30 1987-06-30 Supplementary semiconductor device Pending JPS648662A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62164328A JPS648662A (en) 1987-06-30 1987-06-30 Supplementary semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62164328A JPS648662A (en) 1987-06-30 1987-06-30 Supplementary semiconductor device

Publications (1)

Publication Number Publication Date
JPS648662A true JPS648662A (en) 1989-01-12

Family

ID=15791078

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62164328A Pending JPS648662A (en) 1987-06-30 1987-06-30 Supplementary semiconductor device

Country Status (1)

Country Link
JP (1) JPS648662A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100758759B1 (en) * 2004-03-02 2007-09-14 내셔날 인스티튜트 오브 어드밴스드 인더스트리얼 사이언스 앤드 테크놀로지 Semiconductor integrated circuit and method of manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100758759B1 (en) * 2004-03-02 2007-09-14 내셔날 인스티튜트 오브 어드밴스드 인더스트리얼 사이언스 앤드 테크놀로지 Semiconductor integrated circuit and method of manufacturing the same

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