JPS648751U - - Google Patents
Info
- Publication number
- JPS648751U JPS648751U JP1987102391U JP10239187U JPS648751U JP S648751 U JPS648751 U JP S648751U JP 1987102391 U JP1987102391 U JP 1987102391U JP 10239187 U JP10239187 U JP 10239187U JP S648751 U JPS648751 U JP S648751U
- Authority
- JP
- Japan
- Prior art keywords
- chips
- bumps
- main surface
- main surfaces
- main
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
Landscapes
- Semiconductor Integrated Circuits (AREA)
Description
第１図ａ〜ｄは本考案の一実施例の構造を説明
するためにその製造方法を工程順に示す模式的平
面図、第２図ａ〜ｄは第１図ａ〜ｄのそれぞれの
Ａ−Ａ線断面図、第３図はＩＣメモリパツケージ
を搭載した従来のＩＣメモリモジユールの平面図
、第４図はフリツプチツプ接続技術を用いた従来
のＩＣメモリモジユールの平面図、第５図は第４
図の一部分の断面図である。
１……ＩＣメモリパツケージ、１ａ……ＩＣメ
モリチツプ、２……バイパスコンデンサ、３，３
ａ，３ｂ，３ｃ……配線基板、４，４ａ……外部
端子、５……半田、６ａ……フリツプチツプバン
ド、６ｂ……部品搭載ランド、６ｃ……端子ラン
ド、７……外装樹脂。
1A to 1D are schematic plan views showing the manufacturing method in order of steps to explain the structure of an embodiment of the present invention, and FIGS. 2A to 2D are respectively A-D of FIGS. 3 is a plan view of a conventional IC memory module equipped with an IC memory package, FIG. 4 is a plan view of a conventional IC memory module using flip-chip connection technology, and FIG. 5 is a sectional view taken along line A. 4
FIG. 3 is a cross-sectional view of a portion of the figure. 1...IC memory package, 1a...IC memory chip, 2...bypass capacitor, 3, 3
a, 3b, 3c...wiring board, 4, 4a...external terminal, 5...solder, 6a...flip chip band, 6b...component mounting land, 6c...terminal land, 7...exterior resin.
Claims (1)
のＩＣチツプが前記バンプと接続するためにそれ
ぞれの一主面に設けられた端子を介して前記それ
ぞれの一主面にそれぞれ搭載された２枚の配線基
板を有し、前記２枚の配線基板の前記それぞれの
一主面とは反対側のそれぞれの他の主面が互いに
貼り合わせられていることを特徴とするＩＣモジ
ユール。 A plurality of IC chips having bumps for electrical connection are mounted on two main surfaces of each of the plurality of IC chips via terminals provided on one main surface of each of the chips for connection with the bumps. An IC module comprising a substrate, and other main surfaces of the two wiring boards opposite to the respective one main surface are bonded to each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987102391U JPS648751U (en) | 1987-07-02 | 1987-07-02 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987102391U JPS648751U (en) | 1987-07-02 | 1987-07-02 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS648751U true JPS648751U (en) | 1989-01-18 |
Family
ID=31332260
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987102391U Pending JPS648751U (en) | 1987-07-02 | 1987-07-02 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS648751U (en) |
-
1987
- 1987-07-02 JP JP1987102391U patent/JPS648751U/ja active Pending
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