JPS648805U - - Google Patents
Info
- Publication number
- JPS648805U JPS648805U JP10397587U JP10397587U JPS648805U JP S648805 U JPS648805 U JP S648805U JP 10397587 U JP10397587 U JP 10397587U JP 10397587 U JP10397587 U JP 10397587U JP S648805 U JPS648805 U JP S648805U
- Authority
- JP
- Japan
- Prior art keywords
- hole
- path
- conductor
- integrated circuit
- microwave integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 2
- 239000004020 conductor Substances 0.000 claims 4
- 239000003989 dielectric material Substances 0.000 claims 1
Landscapes
- Waveguides (AREA)
- Microwave Amplifiers (AREA)
Description
第１図は本考案のＭＩＣの１実施例の簡略平面
図、第２図は第１図中の―部分の拡大断面図
である。第３図は従来のＭＩＣの簡略平面図であ
る。
１……基板、２，３，４……第１、第２、第３
の導体路、５……接地パターン、６……半導体素
子（チツプ）、１０ａ〜１０ｆ……スルーホール
、１２……分割路。
FIG. 1 is a simplified plan view of one embodiment of the MIC of the present invention, and FIG. 2 is an enlarged cross-sectional view of the portion indicated by - in FIG. FIG. 3 is a simplified plan view of a conventional MIC. 1...Substrate, 2, 3, 4...1st, 2nd, 3rd
5...Grounding pattern, 6...Semiconductor element (chip), 10a to 10f...Through hole, 12...Dividing path.
Claims (1)
３の導体路を配設すると共に之等各導電体路に個
別に接続される３個の電極を有する半導体素子を
設置し、前記基板の他面に、前記第３の導体路に
スルーホールを介して接続される接地パターンを
配設してなるマイクロ波集積回路において、前記
スルーホールは前記第３の導体路に沿つて複数個
設けられており、前記第３の導体路はスルーホー
ル上或いは隣接するスルーホール間に横断する分
割路によつて分断されていることを特徴とするマ
イクロ波集積回路。 A semiconductor element having first, second, and third conductor paths arranged on one surface of a substrate made of a dielectric material and having three electrodes individually connected to each of the conductor paths; In a microwave integrated circuit comprising a ground pattern connected to the third conductor path via a through hole on the other surface of the substrate, the through hole is arranged in plurality along the third conductor path. A microwave integrated circuit, wherein the third conductive path is separated by a dividing path that crosses over the through hole or between adjacent through holes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10397587U JPS648805U (en) | 1987-07-07 | 1987-07-07 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10397587U JPS648805U (en) | 1987-07-07 | 1987-07-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS648805U true JPS648805U (en) | 1989-01-18 |
Family
ID=31335281
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10397587U Pending JPS648805U (en) | 1987-07-07 | 1987-07-07 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS648805U (en) |
-
1987
- 1987-07-07 JP JP10397587U patent/JPS648805U/ja active Pending