JPS6488841A - Buffer memory access control system - Google Patents

Buffer memory access control system

Info

Publication number
JPS6488841A
JPS6488841A JP62246877A JP24687787A JPS6488841A JP S6488841 A JPS6488841 A JP S6488841A JP 62246877 A JP62246877 A JP 62246877A JP 24687787 A JP24687787 A JP 24687787A JP S6488841 A JPS6488841 A JP S6488841A
Authority
JP
Japan
Prior art keywords
value
register
bit
microinstruction
buffer memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62246877A
Other languages
Japanese (ja)
Inventor
Ichirou Shirasaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62246877A priority Critical patent/JPS6488841A/en
Publication of JPS6488841A publication Critical patent/JPS6488841A/en
Pending legal-status Critical Current

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  • Executing Machine-Instructions (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To reduce the overhead of firmware processing to increase the processing speed by indicating whether the value of a base address register should be referred or not in accordance with the value of a modify bit provided in a microinstruction. CONSTITUTION:A modify bit 10 is included besides various operands in the microinstruction. When the bit 10 in the microinstruction is '0', a microprocessor 5 accesses a buffer memory 4 by the address obtained by adding the value in an index address register 2 to the value in a base address register 1 outputted from a gate circuit 3. When the bit 10 is '1', a signal is sent to the circuit 3 and the circuit 3 does not output the value in the register 1 but outputs '0' by this signal, and therefore, the microprocessor 5 accesses the memory 4 by only the value in the register 2, namely, a common address. Thus, areas assigned to respective devices and an area common to all devices are freely accessed without complicated processings of save and store of the register 1.
JP62246877A 1987-09-30 1987-09-30 Buffer memory access control system Pending JPS6488841A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62246877A JPS6488841A (en) 1987-09-30 1987-09-30 Buffer memory access control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62246877A JPS6488841A (en) 1987-09-30 1987-09-30 Buffer memory access control system

Publications (1)

Publication Number Publication Date
JPS6488841A true JPS6488841A (en) 1989-04-03

Family

ID=17155067

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62246877A Pending JPS6488841A (en) 1987-09-30 1987-09-30 Buffer memory access control system

Country Status (1)

Country Link
JP (1) JPS6488841A (en)

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