JPS649638A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS649638A
JPS649638A JP62164428A JP16442887A JPS649638A JP S649638 A JPS649638 A JP S649638A JP 62164428 A JP62164428 A JP 62164428A JP 16442887 A JP16442887 A JP 16442887A JP S649638 A JPS649638 A JP S649638A
Authority
JP
Japan
Prior art keywords
film
interelement
isolating
dielectric
thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62164428A
Other languages
Japanese (ja)
Other versions
JPH0821615B2 (en
Inventor
Masahiro Shimizu
Katsuhiro Tsukamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP62164428A priority Critical patent/JPH0821615B2/en
Priority to US07/213,497 priority patent/US5061654A/en
Publication of JPS649638A publication Critical patent/JPS649638A/en
Priority to US08/296,940 priority patent/US5466623A/en
Publication of JPH0821615B2 publication Critical patent/JPH0821615B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To secure a broad active region and to isolate elements sufficiently without complicated steps, by adopting the steps, by which element isolating insulation films are formed on a semiconductor substrate, and thereafter etching and removing the upper parts of the films. CONSTITUTION:The upper surface parts of a silicon oxide film 3 and an interelement dielectric isolation film 9 on the entire surface of a memory array part are removed by etching. Thus, a thin element isolating film 9a is obtained. In this way, the thickness of the element isolating insulation film 9a at the memory array part (b) becomes thinner than the thickness of the interelement dielectric isolating films 9, which remain in a peripheral circuit part (a). When the thickness of the film is decreased, the tip part of each bird's beak B is removed. Therefore, an initial isolating length lB between the elements at the interelement dielectric isolation film 9 is shortened to an isolation length lbetween the elements at the interelement dielectric isolating film 9a after the etching. an active region C at the memory array part is expanded.
JP62164428A 1987-07-01 1987-07-01 Method for manufacturing semiconductor memory device Expired - Fee Related JPH0821615B2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP62164428A JPH0821615B2 (en) 1987-07-01 1987-07-01 Method for manufacturing semiconductor memory device
US07/213,497 US5061654A (en) 1987-07-01 1988-06-30 Semiconductor integrated circuit having oxide regions with different thickness
US08/296,940 US5466623A (en) 1987-07-01 1994-08-29 Method of making semiconductor integrated circuit having isolation oxide regions with different thickness

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62164428A JPH0821615B2 (en) 1987-07-01 1987-07-01 Method for manufacturing semiconductor memory device

Publications (2)

Publication Number Publication Date
JPS649638A true JPS649638A (en) 1989-01-12
JPH0821615B2 JPH0821615B2 (en) 1996-03-04

Family

ID=15792965

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62164428A Expired - Fee Related JPH0821615B2 (en) 1987-07-01 1987-07-01 Method for manufacturing semiconductor memory device

Country Status (1)

Country Link
JP (1) JPH0821615B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03187224A (en) * 1989-12-15 1991-08-15 Mitsubishi Electric Corp Semiconductor device
US5478759A (en) * 1992-11-26 1995-12-26 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing semiconductor device with retrograde wells

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5984436A (en) * 1982-11-04 1984-05-16 Sanyo Electric Co Ltd Manufacture of semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5984436A (en) * 1982-11-04 1984-05-16 Sanyo Electric Co Ltd Manufacture of semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03187224A (en) * 1989-12-15 1991-08-15 Mitsubishi Electric Corp Semiconductor device
US5478759A (en) * 1992-11-26 1995-12-26 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing semiconductor device with retrograde wells

Also Published As

Publication number Publication date
JPH0821615B2 (en) 1996-03-04

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