JPWO2024252560A1 - - Google Patents

Info

Publication number
JPWO2024252560A1
JPWO2024252560A1 JP2025525526A JP2025525526A JPWO2024252560A1 JP WO2024252560 A1 JPWO2024252560 A1 JP WO2024252560A1 JP 2025525526 A JP2025525526 A JP 2025525526A JP 2025525526 A JP2025525526 A JP 2025525526A JP WO2024252560 A1 JPWO2024252560 A1 JP WO2024252560A1
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2025525526A
Other versions
JPWO2024252560A5 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPWO2024252560A1 publication Critical patent/JPWO2024252560A1/ja
Publication of JPWO2024252560A5 publication Critical patent/JPWO2024252560A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
JP2025525526A 2023-06-07 2023-06-07 Pending JPWO2024252560A1 (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2023/021163 WO2024252560A1 (ja) 2023-06-07 2023-06-07 多層基板の製造方法、及び、半導体装置

Publications (2)

Publication Number Publication Date
JPWO2024252560A1 true JPWO2024252560A1 (ja) 2024-12-12
JPWO2024252560A5 JPWO2024252560A5 (ja) 2026-04-09

Family

ID=93795414

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2025525526A Pending JPWO2024252560A1 (ja) 2023-06-07 2023-06-07

Country Status (3)

Country Link
JP (1) JPWO2024252560A1 (ja)
CN (1) CN121014264A (ja)
WO (1) WO2024252560A1 (ja)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3514647B2 (ja) * 1999-01-05 2004-03-31 三菱樹脂株式会社 多層プリント配線板およびその製造方法
JP4241685B2 (ja) * 2005-07-13 2009-03-18 大日本印刷株式会社 積層装置および積層方法
TW200740334A (en) * 2005-10-20 2007-10-16 Matsushita Electric Industrial Co Ltd Multilayer printed wiring board and its manufacturing method
JP5724806B2 (ja) * 2011-09-30 2015-05-27 株式会社村田製作所 セラミック多層基板及びその製造方法
JP2019036607A (ja) * 2017-08-10 2019-03-07 リード・エレクトロニクス株式会社 回路付きガラス基板含有多層配線板及びその製造方法

Also Published As

Publication number Publication date
CN121014264A (zh) 2025-11-25
WO2024252560A1 (ja) 2024-12-12

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