KR20200083395A - Nonvolatile memory device and method for fabricating the same - Google Patents

Abstract

The present invention relates to a nonvolatile memory device and a fabricating method thereof. The present invention provides a nonvolatile memory device which reduces a resistance and a resistance component at a portion connecting wiring to a channel. The nonvolatile memory device according to the present invention comprises: a substrate; a lower laminated structure including a plurality of lower conductive electrodes laminated in a first direction on the substrate; an upper laminated structure including an upper conductive electrode on the lower laminated structure; a lower channel structure including a lower channel membrane penetrating through the lower laminated structure to be extended in the first direction; and an upper channel structure including an upper channel membrane penetrating through the upper laminated structure to be extended in the first direction, wherein the upper channel membrane is in contact with the lower channel membrane, the width of the lower channel membrane in a second direction is greater than that of the upper channel membrane in the second direction on a boundary between the lower channel membrane and the upper channel membrane, the upper channel membrane is composed of monocrystalline silicon, and the lower channel membrane includes polycrystalline silicon.

Description

Non-volatile memory device and its manufacturing method{NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME}

The present invention relates to a nonvolatile memory device and a method for manufacturing the same, and more particularly, the present invention relates to a nonvolatile memory device in which the upper channel film is formed of single crystal silicon and a method for manufacturing the same.

The semiconductor memory device can be roughly classified into a volatile memory device and a nonvolatile memory device.

In order to meet the excellent performance and low price required by consumers, it is required to increase the integration density of semiconductor devices. In the case of a semiconductor device, since the integration degree is an important factor in determining the price of a product, an increase in integration degree is particularly required. Therefore, in recent years, three-dimensional memory devices in which unit memory cells are vertically arranged have been developed.

In a three-dimensional memory device in which memory cells are vertically disposed, deterioration of electrical characteristics in a channel film is a major issue as generations continue, and various processes have been developed to overcome this.

An object of the present invention is to provide a nonvolatile memory device that reduces resistance and resistance components of a channel film disposed on a string selection line.

The problem to be solved by the present invention is to provide a method of manufacturing a nonvolatile memory device that reduces resistance and resistance components of a channel film disposed on a string selection line.

The problems to be solved by the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

Non-volatile memory device according to some embodiments of the present invention for achieving the above technical problem, on a substrate, a substrate, a lower stacked structure including a plurality of lower conductive electrodes stacked in a first direction, on a lower stacked structure , An upper stacked structure including an upper conductive electrode, a lower channel structure passing through the lower stacked structure, and including a lower channel film extending in a first direction, and an upper channel film extending through the upper stacked structure and extending in a first direction. The upper channel structure, the upper channel film is in contact with the lower channel film, and at the boundary between the lower channel film and the upper channel film, the width of the lower channel film in the second direction is greater than the width of the upper channel film in the second direction. The large, upper channel film is formed of monocrystalline silicon, and the lower channel film contains polycrystalline silicon.

A method of manufacturing a nonvolatile memory according to some embodiments of the present invention for achieving the above technical problem, forms a lower mold structure in which a mold insulating film and a sacrificial insulating film are alternately stacked on a substrate, penetrates the lower mold structure, A lower channel structure including a lower channel film is formed, an upper mold structure including an upper conductive film is formed on the lower mold structure, an upper channel hole is formed through the upper mold structure, and an upper channel hole is exposed, and an upper channel hole is formed. In the channel hole, forming a free upper channel film in contact with the lower channel film, the pro upper channel film is formed of amorphous silicon, and changing the free upper channel film through a single crystallization process to form an upper channel film in the upper channel hole The single crystallization process is a method of manufacturing a nonvolatile memory device using one of a metal induced lateral crystallization (MILC) process, a laser thermal annealing process, and a selective epitaxial growth (SEG) process. Includes.

Specific details of other embodiments are included in the detailed description and drawings.

1 is an exemplary circuit diagram for describing a nonvolatile memory device in accordance with some embodiments.
2 is a cross-sectional view illustrating a nonvolatile memory device in accordance with some embodiments.
3A to 3D are various views for describing the region P in FIG. 2.
4A and 4B are various views for describing the Q region of FIG. 2.
5 is a cross-sectional view illustrating a nonvolatile memory device in accordance with some embodiments.
6A to 6D are various views for describing the P region of FIG. 5.
7 is a cross-sectional view illustrating a nonvolatile memory device in accordance with some embodiments.
8 to 13 are intermediate stage diagrams for describing a nonvolatile memory device according to some embodiments.

1 is an exemplary circuit diagram for describing a nonvolatile memory device in accordance with some embodiments.

Referring to FIG. 1, a memory cell array of a nonvolatile memory device according to some embodiments includes a common source line (CSL), a plurality of bit lines (BL0-BL2), and a common source line (CSL) and bit lines ( BL0-BL2) may include a plurality of cell strings CSTR.

A plurality of cell strings CSTR may be connected to each of the bit lines BL0-BL2 in parallel. The plurality of cell strings CSTR may be commonly connected to the common source line CSL. That is, a plurality of cell strings CSTR may be disposed between the plurality of bit lines BL0-BL2 and one common source line CSL. The common source lines CSL may be arranged in two dimensions in plural. Here, the same voltage may be applied to the common source lines CSL, or each of the common source lines CSL may be electrically controlled.

For example, each cell string CSTR may include a string select transistor SST, series-connected memory cells MCT, and a ground select transistor GST. In addition, each of the memory cells MCT includes a data storage element.

For example, each cell string CSTR may include a string select transistor SST connected in series with the bit lines BL0-BL2. The ground select transistor GST may be connected to the common source line CSL. The memory cells MCT may be connected in series between the string select transistor SST and the ground select transistor GST.

Furthermore, each cell string CSTR may further include a dummy cell DMCT connected between the string select transistor SST and the memory cell MCT.

Although not shown in the drawing, the dummy cell DMCT may be connected between the ground selection transistor GST and the memory cell MCT. As another example, the ground select transistor GST in each cell string CSTR may be composed of a plurality of MOS transistors connected in series. As another example, each cell string CSTR may include a plurality of string select transistors connected in series. As another example, each cell string CSTR may further include an erase control transistor disposed between the bit lines BL0-BL2 and the string select transistor SST. The erase control transistor may be connected in series with the string selection transistor SST.

According to some embodiments, the string select transistor SST may be controlled by the string select line SSL. The memory cells MCT may be controlled by a plurality of word lines WL0-WLn, and the dummy cells DMCT may be controlled by a dummy word line DWL. Also, the ground select transistor GST may be controlled by the ground select line GSL. The common source line CSL may be commonly connected to the sources of the ground selection transistors GST.

One cell string CSTR may be formed of a plurality of memory cells MCT having different distances from the common source lines CSL. In addition, a plurality of word lines WL0-WLn and DWL may be disposed between the common source lines CSL and the bit lines BL0-BL2.

The gate electrodes of the memory cells MCT, which are disposed at substantially the same distance from the common source lines CSL, may be in an equipotential state by being commonly connected to one of the word lines WL0-WLn and DWL. Alternatively, even if the gate electrodes of the memory cells MCT are disposed at substantially the same level from the common source lines CSL, the gate electrodes disposed in different rows or columns can be independently controlled.

The ground select lines GSL0-GSL2 and the string select lines SSL may extend in the same direction as, for example, the word lines WL0-WLn and DWL. The ground select lines GSL0-GSL2 and the string select line SSL that are disposed at substantially the same level from the common source lines CSL may be electrically separated from each other.

Although not shown in the figure, when the cell string CSTR includes an erase control transistor, the erase control transistors can be controlled by a common erase control line. The erase control transistors generate a gate induced drain leakage (GIDL) during an erase operation of the memory cell array. That is, the erase control transistors may be GIDL transistors.

2 is a cross-sectional view illustrating a nonvolatile memory device in accordance with some embodiments. 3A to 3D are various views for describing the region P in FIG. 2. 4A and 4B are various views for describing the Q region of FIG. 2.

2 to 4B, a nonvolatile memory device according to some embodiments includes a substrate 100, a lower stack structure ST_B, an upper stack structure ST_U, a lower channel structure CS_B, and an upper portion formed of single crystal silicon. An upper channel structure CS_U including the channel layer 130_U and a plurality of bit lines BL may be included.

The substrate 100 may include one of a silicon substrate, a silicon germanium substrate, a germanium substrate, a silicon germanium on insulator (SGOI), a silicon-on-insulator (SOI), and a germanium-on-insulator (GOI). Alternatively, the substrate 100 may include a semiconductor material such as indium antimony, a lead tellurium compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but is not limited thereto.

The horizontal conductive substrate 150 may be disposed on the substrate 100. The horizontal conductive substrate 150 may be a common source plate. That is, the horizontal conductive substrate 150 may serve as the common source line CSL of FIG. 1.

The horizontal conductive substrate 150 may include at least one of a conductive semiconductor film, a metal silicide film, and a metal film. When the horizontal conductive substrate 150 includes a conductive semiconductor film, the horizontal conductive substrate 150 is, for example, silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium Arsenic (InGaAs), aluminum gallium arsenide (AlGaAs), or a combination thereof. The horizontal conductive substrate 150 may have a crystal structure including at least one selected from single crystal, amorphous and polycrystalline. The horizontal conductive substrate 150 may include at least one of p-type impurities, n-type impurities, and carbon included in the semiconductor film.

The stacked structure ST may be disposed on the horizontal conductive substrate 150. The stacked structure ST may include a lower stacked structure ST_B and an upper stacked structure ST_U.

The lower stack structure ST_B may include a plurality of lower conductive electrodes GSL, WL ₀ -WL _n and DWL stacked in the first direction D1 and a plurality of inter-electrode insulating layers 120 and 125. The inter-electrode insulating layers 120 and 125 are disposed between the lower conductive electrodes GSL and WL ₀ to WL _n and DWL spaced apart in the first direction D1.

The plurality of lower conductive electrodes GSL, WL ₀ -WL _n , and DWL may include a ground selection line GSL, a plurality of word lines WL ₀ -WL _n , and a dummy word line DWL. The ground selection line GSL, the plurality of word lines WL ₀ to WL _n , and the dummy word line DWL may be sequentially stacked on the substrate 100.

The upper stacked structure ST_U may include the upper conductive electrode SSL and the interlayer insulating layer 126 stacked in the first direction D1 on the lower stacked structure ST_B. The inter-structure insulating layer 126 is disposed between the upper conductive electrode SSL and the lower conductive electrode disposed on the top of the lower stacked structure ST_B, for example, a dummy word line DWL.

In FIG. 2, only five word lines WL ₀ to WLn are illustrated on the ground selection line GSL, but this is for convenience of description and is not limited thereto. In addition, the lower conductive electrode disposed on the top of the lower stacked structure ST_B is illustrated as a dummy word line DWL, but is not limited thereto. When the cell string CSTR of FIG. 1 does not include the dummy cell DMCT, the lower conductive electrode disposed on the top of the stack structure ST may be a word line WL _n .

The lower stacked structure ST_B may include a first lower sub stacked structure ST_B_1 and a second lower sub stacked structure ST_B_2 on the first lower sub stacked structure ST_B_1. The first lower sub-stack structure ST_B_1 may include a ground selection line GSL and some word lines WL ₀ -WL _k . The second lower sub-stack structure ST_B_2 may include the remaining word lines WL _k+1 -WL _n and a dummy word line DWL. Here, n is a natural number greater than k.

The inter-electrode insulating layer between the word line WL _k positioned at the top of the first lower sub-layered structure ST_B_1 and the word line WL _k+1 positioned at the bottom of the second lower sub-layered structure ST_B_2 ( 125) is thicker than the thickness of the inter-electrode insulating layer 120 in the first lower sub-layered structure ST_B_1 and the second lower sub-layered structure ST_B_2.

The upper conductive electrode SSL may be disposed on the upper stacked structure ST_U. For example, the upper conductive electrode SSL may serve as the string selection line of FIG. 1. The upper conductive electrode SSL may be included in the string select transistor SST of FIG. 1. As another example, a portion of the upper conductive electrode SSL may serve as the string selection line of FIG. 1. The rest of the upper conductive electrode SSL is not shown in FIG. 1, but an erase control line included in the erase control transistor may be used. The upper conductive electrode SSL is thicker than the thickness of the lower conductive electrodes GSL, WL ₀ -WL _n , DWL.

The upper conductive electrode SSL may include an upper surface opposite to the lower stacked structure ST_B, and a lower surface facing the lower stacked structure ST_B. The lower surface of the upper conductive electrode looks at the dummy word line DWL. An inter-structure insulating layer 126 may be disposed between the lower surface of the upper conductive electrode and the upper surface of the dummy word line DWL. The inter-structure insulating film 126 is thicker than the thickness of the inter-electrode insulating film 120 in the first lower sub-layered structure ST_B_1 and the second lower sub-layered structure ST_B_2.

The lower conductive electrode (GSL, WL ₀ -WL _n , DWL) includes a different material from the upper conductive electrode (SSL). For example, the lower conductive electrode (GSL, WL ₀ -WL _n , DWL) may include a metallic material, and the upper conductive electrode (SSL) may include a semiconductor material. The lower conductive electrodes GSL, WL ₀ -WL _n , and DWL may be formed in different manufacturing processes from the upper conductive electrode SSL.

The lower conductive electrodes (GSL, WL ₀ -WL _n , DWL) may include, for example, metal such as tungsten (W), cobalt (Co), nickel (Ni), but the type of metal is not limited thereto. Does not. 3A to 4B, the lower conductive electrodes GSL, WL ₀ -WL _n , and DWL are illustrated as being formed of a multi-layer film, but are for convenience of description and are not limited thereto.

The lower conductive electrodes GSL, WL ₀ -WL _n , and DWL may include a barrier conductive layer BML and a peeling conductive layer FML. The peeling conductive film FML is disposed on the vertical lower channel film 130_BV. The barrier conductive layer BML is disposed between the filling conductive layer FML and the vertical lower channel layer 130_BV.

The barrier conductive layer (BML) may include at least one of metal, metal nitride, metal carbonitride, and two-dimensional (2D) material. For example, the two-dimensional material can be a metallic material and/or a semiconducting material. The 2D material may include a 2D allotrope or a 2D compound. The peeling conductive film FML may include metals such as tungsten (W), cobalt (Co), and nickel (Ni), but the type of the metal is not limited thereto.

The upper conductive electrode SSL may include, for example, at least one of silicon (Si), germanium (Ge), and silicon germanium (SiGe). Alternatively, the upper conductive electrode (SSL) may include at least one of III-V compound semiconductors. The upper conductive electrode may have a crystal structure including at least one selected from single crystal, amorphous and polycrystalline. The upper conductive electrode SSL may further include at least one of p-type impurities, n-type impurities, and carbon included in the semiconductor film.

The inter-electrode insulating films 120 and 125 and the inter-structure insulating film 126 may include, for example, silicon oxide, but are not limited thereto.

The channel structure CS extends in the first direction D1. The channel structure CS may penetrate the lower stacked structure ST_B and the upper stacked structure ST_U. The channel structure CS may include an upper channel structure CS_U disposed in the upper stack structure ST_U and a lower channel structure CS_B disposed in the lower stack structure ST_B.

The size of the upper channel structure CS_U is smaller than the size of the lower channel structure CS_B. That is, the width of the upper channel structure CS_U in the second direction D2 is smaller than the width of the lower channel structure CS_B in the second direction D2. That is, at the boundary between the upper channel layer 130_U and the lower channel layer 130_B, the width of the lower channel layer 130_B in the second direction D2 is greater than the width of the upper channel layer 130 in the second direction D2. Big.

As the upper channel structure CS_U moves away from the bit line BL in the first direction D1 toward the lower channel structure CS_B, the width in the second direction D2 may decrease.

The bit line pad BL_PAD is disposed on the upper channel structure CS_U. The bit line pad BL_PAD may include a conductive material. For example, the bit line pad BL_PAD may include a semiconductor material doped with n-type impurities.

The lower channel structure CS_B may include a lower channel layer 130_B and a vertical insulating pattern 134. The lower channel layer 130_B may include a channel pad pattern CH_PAD and a vertical lower channel layer 130_BV. The vertical lower channel layer 130_BV may extend in the first direction D1 along the sidewall of the lower channel structure CS_B. The vertical insulation pattern 134 may be a space defined by the channel pad pattern CH_PAD and the vertical lower channel layer 130_BV. The lower channel layer 130_B penetrates the lower stacked structure ST_B. The vertical lower channel layer 130_BV may be electrically connected to the horizontal conductive substrate 150 serving as a common source line.

The channel pad pattern CH_PAD may be positioned between the upper channel layer 130_U and the vertical lower channel layer 130_BV. The channel pad pattern CH_PAD electrically connects the vertical lower channel layer 130_BV and the upper channel layer 130_U.

The vertical lower channel layer 130_BV may include a side wall portion extending in the first direction D1 and a bottom portion connecting the side wall portion of the vertical lower channel layer 130_BV. The sidewall portion of the vertical lower channel layer 130_BV may have a pipe shape having a hollow space therein, for example, a cylindrical shape or a macaroni shape.

The lower channel layer 130_B may be disposed in the lower stacked structure ST_B. The vertical lower channel layer 130_BV may extend along sidewalls of the word lines WL ₀ to WL _n , the ground selection line GSL, and the dummy word line DWL included in the stack structure ST.

The upper channel layer 130_U may penetrate the upper stacked structure ST_U and contact the bit line pad BL_PAD. The upper channel layer 130_U and the vertical lower channel layer 130_BV may extend in the first direction D1, respectively. Depending on the structure, it may extend while having a slope with respect to the first direction D1. The channel pad pattern CH_PAD may extend in the second direction D2.

The vertical lower channel layer 130_BV may include, for example, a semiconductor material such as silicon (Si), germanium (Ge), or a mixture thereof. Alternatively, the vertical lower channel layer 130_BV may include a semiconductor material such as a metal oxide semiconductor material, an organic semiconductor material, and a carbon nano structure. The upper channel layer 130_U may be formed of single crystal silicon.

3A to 3D, the lower channel layer 130_B may include a channel pad pattern CH_PAD positioned above the vertical lower channel layer 130_BV. The channel pad pattern CH_PAD may be positioned between the vertical lower channel layer 130_BV and the upper channel layer 130_U.

In a nonvolatile memory device according to some embodiments, the channel pad pattern CH_PAD may include polycrystalline silicon. On the other hand, the upper channel layer 130_U may include single crystal silicon.

The channel pad pattern CH_PAD electrically connects the upper channel layer 130_U and the vertical lower channel layer 130_BV. The lower surface of the channel pad pattern CH_PAD is connected to the vertical lower channel layer 130_BV, and the upper surface of the channel pad pattern CH_PAD is connected to the lower surface of the upper channel layer 130_U.

The channel pad pattern CH_PAD may include, for example, a semiconductor material such as silicon (Si), germanium (Ge), or a mixture thereof. In a nonvolatile memory device according to some embodiments, the lower channel layer 130_BV may include polycrystalline silicon.

3A and 3B, the upper channel layer 130_U may have a pillar shape filled in.

3C and 3D, the upper channel structure CS_U may include a vertical insulation pattern 134. The vertical insulation pattern 134 may include, for example, at least one of silicon oxide, silicon oxynitride, and a low dielectric constant material, but is not limited thereto. The upper channel layer 130_U may include a side wall portion extending in the first direction D1 and a bottom portion connecting the side wall portion of the upper channel layer 130_U. The sidewall portion of the upper channel layer 130_U may have a pipe shape having a hollow space therein, for example, a cylindrical shape or a macaroni shape.

The nonvolatile memory device according to some embodiments may further include a silicide layer 140 extending along an upper surface of the channel pad pattern CH_PAD. The silicide layer 140 may be positioned at the boundary between the upper channel layer 130_U and the channel pad pattern CH_PAD. The boundary between the upper channel layer 130_U and the channel pad pattern CH_PAD is between the lower conductive electrode closest to the upper conductive electrode SSL, for example, the upper surface of the dummy word line DWL and the lower surface of the upper conductive electrode SSL. Can be located at The silicide film 140 includes a silicide material, and may include, for example, at least one of nickel silicide (NiSi), palladium silicide (PdSi), and platinum silicide (PtSi), but is not limited thereto.

3A and 3C, a silicide layer 140 may be formed at the boundary between the upper channel layer 130_U and the channel pad pattern CH_PAD.

Referring to FIGS. 3B and 3D, the silicide film 140 may not be formed.

The upper channel structure CS_U may include an upper channel layer 130_U and an upper channel insulating layer 132_UGI disposed on the upper conductive electrode SSL. The lower channel structure CS_B is between the vertical lower channel layer 130_BV and the plurality of lower conductive electrodes GSL, WL ₀ -WL _n , DWL, and between the lower channel layer 130_BV and the inter-electrode insulating layer 120. The lower channel insulating layer 132_BGI may be disposed. The upper channel insulating layer 132_UGI and the lower channel insulating layer 132_BGI may extend along the upper channel layer 130_U and the vertical lower channel layer 130_BV.

2 to 4B, the lower channel insulating film 132_BGI includes, for example, a tunnel insulating film 132a, a charge storage film 132b, and a blocking insulating film 132c sequentially disposed on the vertical lower channel film 130_BV. can do. The tunnel insulating film 132a, the charge storage film 132b, and the blocking insulating film 132c are merely exemplary, but are not limited thereto.

The tunnel insulating layer 132a may include, for example, silicon oxide or a high-k material (eg, aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ )). The charge storage layer 132b may include, for example, silicon nitride. The blocking insulating layer 132c may include, for example, silicon oxide or a high-k material (eg, aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ )). In a nonvolatile memory device according to some embodiments, the tunnel insulating layer 132a and the blocking insulating layer 132c may include silicon oxide.

A horizontal insulating pattern HP may be disposed between the lower conductive electrodes GSL, WL ₀ -WL _n , and DWL and the lower channel insulating layer 132_BGI. The horizontal insulating pattern HP may include, for example, silicon oxide or a high-k material (eg, aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ )). Unlike illustrated, the horizontal insulating pattern HP may not be disposed between the lower conductive electrodes GSL, WL ₀ -WL _n , and DWL, and the lower channel insulating layer 132_BGI.

In FIG. 4A, the tunnel insulating film 132a, the charge storage film 132b, and the blocking insulating film 132c may be separated under the vertical lower channel film 130_BV. The separated tunnel insulating layer 132a, the charge storage layer 132b, and the blocking insulating layer 132c may expose a portion of the vertical lower channel layer 130_BV. A vertical structure supporting layer 110 may be disposed between the separated tunnel insulating layer 132a, the charge storage layer 132b, and the blocking insulating layer 132c. The vertical structure support layer 110 may electrically connect the horizontal conductive substrate 150 and the vertical lower channel layer 130_BV. The vertical structure support layer 110 may include, for example, a semiconductor material such as silicon (Si), germanium (Ge), or a mixture thereof.

In FIG. 4B, the vertical structure support layer 110 may not be disposed between the horizontal conductive substrate 150 and the stacked structure ST. In this case, the sidewall portion of the vertical lower channel layer 130_BV is not exposed, and the bottom portion of the vertical lower channel layer 130_BV may be exposed. The tunnel insulating layer 132a, the charge storage layer 132b, and the blocking insulating layer 132c between the bottom of the vertical lower channel layer 130_BV and the horizontal conductive substrate 150 may be removed. Through the bottom of the vertical lower channel layer 130_BV, the vertical lower channel layer 130_BV may be electrically connected to the horizontal conductive substrate 150.

2 to 3D, unlike the lower channel insulating film 132_BGI, the upper channel insulating film 132_UGI may include, for example, silicon oxide. In the drawing, the upper channel insulating layer 132_UGI is illustrated as a single layer, but is not limited thereto. The upper channel insulating layer 132_UGI may be formed of multiple layers. For example, in a nonvolatile memory device according to some embodiments, the stacked structure of the upper channel insulating layer 132_UGI may be the same as that of the lower channel insulating layer 132_BGI. As another example, in the nonvolatile memory device according to some embodiments, the upper channel insulating layer 132_UGI may include a stacked structure of silicon oxide and a high dielectric constant insulating layer.

For example, the upper channel insulating layer 132_UGI may contact the upper conductive electrode SSL. That is, a metallic conductive material may not be disposed between the upper channel insulating layer 132_UGI and the upper conductive electrode SSL. As another example, the upper channel insulating layer 132_UGI may further include a conductive liner film including a conductive material between the upper conductive electrodes SSL.

Also, the lower channel insulating layer 132_BGI may not be directly connected to the upper channel insulating layer 132_UGI.

On the upper conductive electrode SSL, the first to third interlayer insulating layers 121, 122, and 123 may be sequentially disposed. A bit line pad BL_PAD may be disposed in the first interlayer insulating layer 121.

The bit line BL may be disposed on the upper conductive electrode SSL. The bit line BL may be elongated in the second direction D2. The bit line BL may be electrically connected to at least one of the upper channel layers 130_U. The bit line BL may be formed on the third interlayer insulating layer 123. The bit line BL may be electrically connected to the bit line pad BL_PAD through the bit line plug BLPG.

5 is a cross-sectional view illustrating a nonvolatile memory device in accordance with some embodiments. 6A to 6D are various views for describing the P region of FIG. 5. For convenience of description, description will be made focusing on differences from those described with reference to FIGS. 2 to 4B.

5 to 6D, in a nonvolatile memory device according to some embodiments, the lower channel layer 130_B may include a channel pad pattern CH_PAD formed of single crystal silicon. The lower channel layer 130_B includes a channel pad pattern CH_PAD formed of single crystal silicon and a vertical lower channel layer 130_BV.

The channel pad pattern CH_PAD may be formed at the same level as the upper channel layer 130_U. Here, "same level" means that formed by the same manufacturing process.

The channel pad pattern CH_PAD and the upper channel layer 130_U may have an integral structure.

Unlike in FIGS. 2 to 3D, the lower channel insulating layer 132_BGI may extend in a first direction D1 along a side wall of the channel pad pattern CH_PAD and a vertical lower channel film 130_BV. Depending on the structure, it may extend while having a slope with respect to the first direction D1.

Referring to FIGS. 6A and 6C, a silicide layer 140 extending along a lower surface of the channel pad pattern CH_PAD may be further included. The silicide layer 140 may be positioned at a boundary between the channel pad pattern CH_PAD and the vertical lower channel layer 130_BV.

6A and 6B, the upper channel layer 130_U may have a pillar shape filled with a layer.

6C and 6D, the upper channel structure CS_U may include a vertical insulation pattern 134. The vertical insulation pattern 134 may be formed in the channel pad pattern CH_PAD. The vertical insulation pattern 134 may include, for example, at least one of silicon oxide, silicon oxynitride, and a low dielectric constant material, but is not limited thereto. The upper channel layer 130_U may include sidewall portions extending in the first direction D1. The channel pad pattern CH_PAD includes a side wall portion extending in the first direction D1, a bottom portion connecting the side wall portions of the channel pad pattern CH_PAD, and a side wall portion of the channel pad pattern CH_PAD and an upper channel layer 130_U. It may include a connecting portion connecting the side wall portion. The sidewall portion of the upper channel layer 130_U and the sidewall portion of the channel pad pattern CH_PAD may have a cylindrical shape therein.

6A and 6C, the silicide layer 140 may extend along the lower surface of the channel pad pattern CH_PAD. That is, the silicide layer 140 is positioned at the boundary between the channel pad pattern CH_PAD and the vertical lower channel layer 130_BV.

7 is a diagram for describing a nonvolatile memory device according to some embodiments. For convenience of description, description will be made focusing on differences from those described with reference to FIGS. 2 to 4B.

Referring to FIG. 7, a nonvolatile memory device according to some embodiments may include a peripheral logic structure PS and a cell array structure CAS.

The peripheral logic structure PS may include a peripheral circuit PTR, a lower connection wiring body PW, and a peripheral logic insulating layer 101.

The peripheral circuit PTR may be formed on the substrate 100. The peripheral circuit PTR may be circuits that operate the cell array structure CAS.

The peripheral logic insulating layer 101 may be formed on the substrate 100. The peripheral logic insulating layer 101 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and low dielectric constant materials.

The lower connection wiring body PW may be formed in the peripheral logic insulating layer 101. The lower connection wiring body PW may be connected to the peripheral circuit PTR.

The cell array structure CAS may be disposed on the peripheral logic structure PS. The cell array structure CAS may include a lower stack structure ST_B, an upper conductive electrode SSL, a plurality of channel structures CS, and a plurality of bit lines BL.

The horizontal conductive substrate 150 may extend along the upper surface of the peripheral logic structure PS.

Unlike illustrated, the peripheral logic structure PS may be disposed on the bit line BL. In other words, the bit line BL may be disposed between the upper conductive electrode SSL and the peripheral logic structure PS.

8 to 13 are intermediate stage diagrams for describing a nonvolatile memory device according to some embodiments. For reference, FIGS. 8 to 13 may be diagrams corresponding to the P portion of FIG. 2.

Referring to FIG. 8, a mold structure MS in which an inter-electrode insulating film 120 and a sacrificial insulating film ILD_SC are alternately stacked may be formed on the substrate 100.

In the mold structure MS, a lower channel structure CS_B penetrating the mold structure MS may be formed. The lower channel structure CS_B includes a lower channel layer 130_B, a lower channel insulating layer 132_BGI, and a vertical insulating pattern 134. The lower channel layer 130_B includes a vertical lower channel layer 130_BV and a channel pad pattern CH_PAD.

Subsequently, the inter-structure insulating film 126, the upper conductive electrode SSL, and the first interlayer insulating film 121 are sequentially stacked on the lower channel structure CS_B.

An upper channel hole CH_H may be formed in the upper conductive electrode SSL. The upper channel hole CH_H may penetrate the first interlayer insulating layer 121, the upper conductive electrode SSL and the inter-layer insulating layer 126. The upper channel hole CH_H may expose the channel pad pattern CH_PAD in the lower channel structure CS_B.

Referring to FIG. 9, an upper channel insulating layer 132_UGI may be formed along sidewalls of the upper channel hole CH_H. Although the upper channel insulating layer 132_UGI is illustrated as a single layer in the drawing, it is not limited thereto. The upper channel insulating film 132_UGI may be a multi-layer film, or may have the same layered structure as the lower channel insulating film 132_UGI.

Subsequently, a free upper channel layer 130_PR may be formed on the upper channel insulating layer 132_UGI in the upper channel hole CH_H. The free upper channel layer 130_PR may be formed of amorphous silicon. The free upper channel layer 130_PR may fill the inside of the upper channel hole CH_H.

Referring to FIG. 10, a metal film 141 is formed on the free upper channel film 130_PR and the first interlayer insulating film 121. The metal film 141 extends in the second direction D2. The metal film 141 may include, for example, nickel (Ni), palladium (Pd), and platinum (Pt) metals, but the type of the metal is not limited thereto.

Referring to FIG. 11, a silicide film 140 is formed under the metal film 141, that is, between the metal film 141 and the free upper channel film 130_PR through a silicide process.

Referring to FIG. 12, the metal film 141 remaining after the silicidation process may be removed.

Referring to FIG. 13, through a single crystallization process, the free upper channel film 130_PR may be changed to an upper channel film 130_U.

The upper channel film 130_U formed through the single crystallization process is formed of single crystal silicon. The monocrystallization process may use a metal induced lateral crystallization (MILC) process, but is not limited thereto. When the MILC process is used, the amorphous silicon is changed to single crystal silicon while the silicide film 140 descends along the sidewall of the free upper channel film 130_PR. The silicide film 140 is stopped between the lower channel film 130_BV and the free upper channel film 130_PR.

Unlike the above, the single crystallization process may use a laser thermal annealing process. In this case, the silicide film 140 may not be formed.

Although not shown in the drawing, in order to provide a nonvolatile memory device as shown in FIGS. 3C and 3D, a vertical insulating pattern 134 filling a portion of the upper channel hole CH_H is formed on the upper free channel layer 130_PR. Can be. The upper free channel layer 130_PR may include a side wall portion extending in the first direction D1 and a bottom portion connecting the side wall portion of the upper free channel layer 130_PR. The sidewall portion of the upper free channel layer 130_PR may have a pipe shape having a hollow space therein, for example, a cylindrical shape or a macaroni shape.

The sidewall portion and the bottom portion of the upper free channel layer 130_PR may be changed from amorphous silicon to single crystal silicon through the single crystallization process described above.

Subsequently, although not illustrated in the drawing, a bit line pad BL_PAD in contact with the upper channel layer 130_U may be formed on the vertical insulating pattern 134 or the upper channel layer 130_U.

Referring to FIG. 2, a second interlayer insulating layer 122 covering the bit line pad BL_PAD may be formed on the first interlayer insulating layer 121. A third interlayer insulating layer 123 may be formed on the second interlayer insulating layer 122.

A bit line BL may be formed on the third interlayer insulating layer 123.

Subsequently, the sacrificial insulating film ILD_SC may be replaced with a lower conductive electrode.

In order to provide a nonvolatile memory device as shown in FIG. 6A, although not illustrated in the drawing, a channel pad pattern CH_PAD may not be formed before forming the upper channel hole CH_H. That is, the upper channel hole CH_H may be formed before forming the channel pad pattern CH_PAD. In this case, the upper channel hole CH_H may partially overlap the lower channel structure CS_B. The upper channel hole CH_H may expose the vertical insulating pattern 134 of the lower channel structure CS_B.

Subsequently, an upper channel insulating layer 132_UGI may be formed along sidewalls of the upper channel hole CH_H overlapping the upper channel structure CS_U. An upper channel insulating layer 132_UGI may not be formed on a sidewall of the upper channel hole CH_H overlapping the lower channel structure CS_B.

Subsequently, a free upper channel layer 130_PR may be formed in the upper channel hole CH_H. The free upper channel layer 130_PR may be formed of amorphous silicon.

Subsequently, a metal film 141 is formed on the free upper channel film 130_PR and the first interlayer insulating film 121.

Subsequently, a silicide film 140 is formed through the silicide process, between the lower part of the metal film 141, that is, between the metal film 141 and the free upper channel film 130_PR.

Subsequently, the metal film 141 remaining after the silicidation process may be removed.

Subsequently, through the single crystallization process, the free upper channel film 130_PR may be changed to the upper channel film 130_U. In this case, the channel pad pattern CH_PAD may be formed of single crystal silicon. The monocrystallization process may use a metal induced lateral crystallization (MILC) process, but is not limited thereto.

When using the MILC process, the silicide film 140 descends along the sidewalls of the free upper channel film 130_PR. The silicide film 140 stops at the boundary between the channel pad pattern CH_PAD and the vertical lower channel film 130_BV. The silicide layer 140 may extend along the lower surface of the channel pad pattern CH_PAD.

After forming the free upper channel layer 130_PR, the metal layer 141 may not be formed, and the upper channel layer 130_U may be formed using a laser thermal annealing process.

Although not shown in the drawing, unlike in FIG. 9, the free upper channel layer 130_PR may not be formed inside the upper channel hole CH_H. The upper channel layer 130_U may be formed inside the upper channel hole CH_H without forming the free upper channel layer 130_PR. In this case, a selective epitaxial growth (SEG) process can be used.

The embodiments of the present invention have been described above with reference to the accompanying drawings, but the present invention is not limited to the above embodiments, and may be manufactured in various different forms, and having ordinary knowledge in the technical field to which the present invention pertains. It will be understood that a person can be implemented in other specific forms without changing the technical spirit or essential features of the present invention. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive.

100: substrate ST: laminated structure
120: insulating film CS: channel structure
130_B: lower channel film SSL: upper conductive electrode
130_U: Upper channel film CH_PAD: Channel pad pattern
140: silicide film 134: vertical insulation pattern

Claims (10)

Board;
A lower stacked structure including a plurality of lower conductive electrodes stacked on the substrate in a first direction;
An upper stacked structure including an upper conductive electrode on the lower stacked structure;
A lower channel structure including a lower channel film extending through the lower layered structure and extending in the first direction; And
And an upper channel structure including an upper channel film extending in the first direction through the upper stack structure.
The upper channel film is in contact with the lower channel film,
At a boundary between the lower channel film and the upper channel film, a width in the second direction of the lower channel film is greater than a width in the second direction of the upper channel film,
The upper channel film is formed of single crystal silicon,
The lower channel film is a non-volatile memory device comprising polycrystalline silicon. According to claim 1,
The upper conductive electrode includes a polycrystalline silicon conductive film,
The lower conductive electrode is a non-volatile memory device including a metallic conductive film. According to claim 1,
The plurality of lower conductive electrodes include a first lower conductive electrode closest to the upper conductive electrode,
A boundary between the lower channel layer and the upper channel layer is located between the upper surface of the first lower conductive electrode and the lower surface of the upper conductive electrode. According to claim 1,
The lower channel layer includes a channel pad pattern,
The channel pad pattern is a non-volatile memory device comprising polycrystalline silicon. The method of claim 4,
And a silicide film extending along an upper surface of the channel pad pattern. According to claim 1,
The lower channel layer includes a channel pad pattern,
The channel pad pattern is a non-volatile memory device including single crystal silicon. The method of claim 6,
And a silicide film extending along a lower surface of the channel pad pattern. According to claim 1,
The upper channel structure further includes an upper vertical insulation pattern,
The upper channel layer is a non-volatile memory device extending along a sidewall of the upper vertical insulating pattern. According to claim 1,
And a bit line pad disposed on the upper channel layer and including doped impurities. On the substrate, to form a lower mold structure in which a mold insulating film and a sacrificial insulating film are alternately stacked,
Penetrates the lower mold structure, forms a lower channel structure including a lower channel film,
On the lower mold structure, an upper mold structure including an upper conductive film is formed,
An upper channel hole penetrating the upper mold structure and exposing the lower channel film,
In the upper channel hole, a free upper channel film is formed in contact with the lower channel film, and the pro upper channel film is formed of amorphous silicon,
And changing the free upper channel film through a single crystallization process to form an upper channel film in the upper channel hole,
The single crystallization process is a method of manufacturing a nonvolatile memory device using one of a metal induced lateral crystallization (MILC) process, a laser thermal annealing process, and a selective epitaxial growth (SEG) process.

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