KR910020732A - 의사 스태틱 ram의 제어회로 - Google Patents

의사 스태틱 ram의 제어회로 Download PDF

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Publication number
KR910020732A
KR910020732A KR1019910008047A KR910008047A KR910020732A KR 910020732 A KR910020732 A KR 910020732A KR 1019910008047 A KR1019910008047 A KR 1019910008047A KR 910008047 A KR910008047 A KR 910008047A KR 910020732 A KR910020732 A KR 910020732A
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KR
South Korea
Prior art keywords
signal
control
control circuit
control signal
static ram
Prior art date
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Application number
KR1019910008047A
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English (en)
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KR950007141B1 (ko
Inventor
나오카즈 미야와키
Original Assignee
아오이 죠이치
가부시키가이샤 도시바
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Publication of KR910020732A publication Critical patent/KR910020732A/ko
Application granted granted Critical
Publication of KR950007141B1 publication Critical patent/KR950007141B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40615—Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)

Abstract

내용 없음

Description

의사 스태틱 RAM의 제어회로
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 제1실시예에 따른 구성을 도시해 놓은 회로도, 제3도는 제1도의 회로동작을 설명하기 위한 타이밍챠트, 제4도는 CS대기모드를 설명하기 위한 타이밍챠트.

Claims (1)

  1. 칩이네이블신호가 공급되고, 이 칩이네이블신호의 의 레벨변화에 동기해서 침선택신호를 래치하기 위해 이용되는 제1제어신호군을 발생시키는 제1제어회로(1)와, 칩선택신호(CS) 및 상기 제1제어신호군이 공급되고, 이 제1제어신호군에 근거해서 칩선택신호를 래치하며, 이 래치신호에 따른 제2제어신호를 발생시키는 제2제어회로(2) 및, 기록네이블신호및 상기 제1제어신호군의 일부신호와 상기 제2제어신호가 공급되고, 제1제어신호군의 일부신호와 상기 제2제어신호에 따라서 기록이네이블신호의 제어를 행하여, 내부에서 사용되는 데이터기록제어용 제3제어신호를 발생시키는 제3제어회로(3)를 구비하여 구성된 것을 특징으로 하는 의사 스태틱 RAM의 제어회로.
    ※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.
KR1019910008047A 1990-05-21 1991-05-17 의사 스태틱 ram의 제어회로 Expired - Fee Related KR950007141B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2-130893 1990-05-21
JP2130893A JP2744115B2 (ja) 1990-05-21 1990-05-21 疑似スタティックｒａｍの制御回路

Publications (2)

Publication Number Publication Date
KR910020732A true KR910020732A (ko) 1991-12-20
KR950007141B1 KR950007141B1 (ko) 1995-06-30

Family

ID=15045179

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910008047A Expired - Fee Related KR950007141B1 (ko) 1990-05-21 1991-05-17 의사 스태틱 ram의 제어회로

Country Status (5)

Country Link
US (1) US5301164A (ko)
EP (1) EP0458213B1 (ko)
JP (1) JP2744115B2 (ko)
KR (1) KR950007141B1 (ko)
DE (1) DE69116426T2 (ko)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5617551A (en) * 1992-09-18 1997-04-01 New Media Corporation Controller for refreshing a PSRAM using individual automatic refresh cycles
US5590088A (en) * 1993-07-13 1996-12-31 Seiko Epson Corporation Semiconductor memory device with enable signal conversion circuit operative for reducing current consumption
KR0119886B1 (ko) * 1994-07-27 1997-10-17 김광호 반도체 메모리 장치의 모드설정회로 및 그 방법
US5657293A (en) * 1995-08-23 1997-08-12 Micron Technology, Inc. Integrated circuit memory with back end mode disable
KR100431303B1 (ko) 2002-06-28 2004-05-12 주식회사 하이닉스반도체 페이지 기록 모드를 수행할 수 있는 슈도 스태틱램
CN1310299C (zh) * 2003-05-21 2007-04-11 中国科学院计算技术研究所 基于电路静态时延特性的冒险检测和消除方法
US6985385B2 (en) * 2003-08-26 2006-01-10 Grandis, Inc. Magnetic memory element utilizing spin transfer switching and storing multiple bits
KR100695512B1 (ko) 2005-06-30 2007-03-15 주식회사 하이닉스반도체 반도체 메모리 장치
US10332586B1 (en) 2017-12-19 2019-06-25 Micron Technology, Inc. Apparatuses and methods for subrow addressing

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6052513B2 (ja) * 1981-12-02 1985-11-19 富士通株式会社 半導体記憶装置
US4710903A (en) * 1986-03-31 1987-12-01 Wang Laboratories, Inc. Pseudo-static memory subsystem
JPH0644393B2 (ja) * 1986-04-08 1994-06-08 日本電気株式会社 半導体メモリ
JPS63166093A (ja) * 1986-12-26 1988-07-09 Toshiba Corp 半導体メモリの制御回路
JP2569033B2 (ja) * 1987-01-16 1997-01-08 株式会社日立製作所 半導体記憶装置
JP2585602B2 (ja) * 1987-06-10 1997-02-26 株式会社日立製作所 半導体記憶装置
US4879683A (en) * 1987-09-28 1989-11-07 Texas Instruments Incorporated A gaas register file having a plurality of latches
JPH01194194A (ja) * 1988-01-29 1989-08-04 Nec Ic Microcomput Syst Ltd 半導体メモリ装置
JPH01205788A (ja) * 1988-02-12 1989-08-18 Toshiba Corp 半導体集積回路
JP2598081B2 (ja) * 1988-05-16 1997-04-09 株式会社東芝 半導体メモリ

Also Published As

Publication number Publication date
EP0458213A2 (en) 1991-11-27
JP2744115B2 (ja) 1998-04-28
KR950007141B1 (ko) 1995-06-30
EP0458213B1 (en) 1996-01-17
DE69116426D1 (de) 1996-02-29
US5301164A (en) 1994-04-05
DE69116426T2 (de) 1996-06-05
JPH0426986A (ja) 1992-01-30
EP0458213A3 (en) 1993-01-27

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