KR960026257A - 다층 텡스텐 침착 방법 - Google Patents

다층 텡스텐 침착 방법 Download PDF

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KR960026257A
KR960026257A KR1019950067127A KR19950067127A KR960026257A KR 960026257 A KR960026257 A KR 960026257A KR 1019950067127 A KR1019950067127 A KR 1019950067127A KR 19950067127 A KR19950067127 A KR 19950067127A KR 960026257 A KR960026257 A KR 960026257A
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layer
tungsten
deposition rate
deposited
layers
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맨신 머챈트 세일레쉬
쿠마 낸다 애런
쿠마 로이 프라디프
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일라이 웨이스
에이티앤드티 코포레이션
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/42—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a gas or vapour
    • H10P14/43—Chemical deposition, e.g. chemical vapour deposition [CVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/042—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers
    • H10W20/045—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers for deposition from the gaseous phase, e.g. for chemical vapour deposition [CVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H10W20/057—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches by selectively depositing, e.g. by using selective CVD or plating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/069—Manufacture or treatment of conductive parts of the interconnections by forming self-aligned vias or self-aligned contact plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/425—Barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44—Conductive materials thereof
    • H10W20/4403—Conductive materials thereof based on metals, e.g. alloys, metal silicides

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Chemical Vapour Deposition (AREA)
  • Coating By Spraying Or Casting (AREA)
  • Other Surface Treatments For Metallic Materials (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)

Abstract

본 발명은 3개 이상, 바람직하게는 5 내지 7개의 텅스텐 층을 접촉 구멍내에 칩착시켜 층으로 이루어진 플러그를 형성시키므로써, 원치않은 텅스텐 확산 형성을 피하도록 텅스텐 플러그에 관한 것이다. 특히 유용한 실시태양에서, 상기 층은 빠르고 느린 침착 속도로 교대로 침착시킨다.

Description

다층 텅스텐 침착 방법.
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본원에 개시된 방법에 따라(원도우 또는 바이어 레벨에서)텅스텐 플러그를 형성시키는 단계를 나타내는 흐름도이다.

Claims (21)

  1. 3개 이상의 연속적인 텅스텐 층을 접촉 구멍내에 침착시킴을 포함하고; 이때 상기 각 층은 이전이 층을 접착시킨 속도와 상이한 침가속도로 침착되고, 40Å/초보다 큰 빠른 침착속도 및 40Å/초 미만인 느린 침착속도로 교대로 침착되는 텅스텐 플러그 제조 방법.
  2. 제1항에 있어서, 상기 3개 이상의 연속적인 텅스텐 층 각각을 텅스텐 헥사플루오라이드의 소수 환원에 의해 침착시키는 방법.
  3. 제2항에 있어서, 상기 각 층의 침착 공정이 약 10초 내지 약 2분의 비성장 기간만큼 분리되는 방법.
  4. 제1항에 있어서, 5개 이상의 연속적인 텅스텐 층을 침착시키는 방법.
  5. 제3항에 있어서, 상기 5개 이상의 연속적인 텅스텐 층을 침착시키는 방법.
  6. 전도성 층, 상기 전도성 층상에 형성된 절연체 층 및 상기 전도성 층 부분을 노출시키기 위해 절연체 층중에 형성시킨 접촉 구멍을 갖는 기재를 제공하고; 상기 접촉 구멍내에 3개 이상의텅스텐 츠을 침착시켜 적어도 거의 접촉 구멍을 충진시키므로써, 기재의 전도성 층과 또다른 전도성 요소 사이를 전기적으로 연결시킬 수 있는 텅스텐 플러그 형성시킴을 포함하는 전자 장치의 제조 방법.
  7. 제6항에 있어서, 5개 아상의 텅스텐 층을 상기 접촉 구멍내에 침착시키는 방법.
  8. 제6항에 있어서, 상기 연속적인 각 텅스텐 층을 침착시키는 단계가 H2에 의해 WF6를 환원시킴을 포함하는 방법.
  9. 제6항에 있어서, 상기 3개 이상의 각 텅스텐 층을 이전의 층을 침착시킨 속도와 상이한 침착 속도로 침차시키는 방법.
  10. 제9항에 있어서, 상기 3개 이상의 텅스텐 층을 40/초보다 큰 빠른 침착 속도 및 40Å/초 미만의 느린 침착 속도로 교대로 침착시키는 방법.
  11. (a)40Å/초보다 큰 침착 속도로 WF6의 H2환원에 의해 텅스텐 층을 침착시키는 단계; (b) 40Å/초 미만의 침착 속도로 WF6의 H2환원에 의해 텅스텐 층을 침착시키는 단계; (c) 단계(a) 및 (b)를 적어도 거의 접촉 구멍을 충진시키기에 충부한 횟수로 교대로 반복하여, 층으로 이루어진 텅스텐 플러그를 형성시키는 단계를 포함하는, 기재중에 형성된 접촉 구멍내에 텅스텐 플러그를 제조하는 방법.
  12. 제11항에 있어서, 상기 단계 (a)가 기재를 함유하는 챔버의 전체 압력 약 10 내지 약 100토르하에 상기 챔버중으로 H2를 약 6000 내지 약 7500SCCM의 유동속도로 도입하고, 상기 챔버중으로 WF6를 약 300 내지 약 500SCCM의 유동속도로 도입함을 포함하는 방법.
  13. 제11항에 있어서, 상기 단계 (b)가 기재를 함유하는 챔버의 전체 압력 약 10 내지 약 100토르하에 상기 챔버중으로 H2를 약 3000 내지 약 5000SCCM의 유동속도로 도입하고, 상기 챔버중으로 WF6를 약 100 내지 약 300SCCM의 유동속도로 도입함을 포함하는 방법.
  14. 제11항에 있어서, 상기 층으로 이루어진 텅스텐 플러그가 5개 이상의 텅스텐 층을 포함하는 방법.
  15. 텅스텐의 제1층을 제1침착 속도로 WF6의 H2환원에 의해 침착시키고, 텅스텐의 제2층을 상기 제1침착 속도보다 느린 제2침착 속도로 WF6의 H2환원에 의해 침착시키고; 텅스텐 제3층을 상기 제2침착 속도보다 빠른 제3침착 속도로 WF6의 H2환원에 의해 침착시킴을 포함하는, 기재중에 형성된 첩촉 구멍내에 텅스텐 플러그를 제조하는 방법.
  16. 제15항에 있어서, 텅스텐의 제4층을 상기 제3침착 속도보다 느린 제4침착 속도로 WF6의 H2환원에 의해 침착시키고; 텅스텐의 제5층을 상기 제4침착 속도보다 빠른 제5침착 속도로 WF6의 H2환원에 의해 침착시킴을 또한 포함하는 방법.
  17. 제16항에 있어서, 텅스텐의 지6층을 상기 제5침착 속도보다 느린 제6침착 속도로 WF6의 H2환원에 의해 침착시키고; 텅스텐의 제 7층을 상기 제6침착 속도보다 빠른 제7침착 속도로 WF6의 H2환원에 의해 침착시킴을 또한 포함하는 방법.
  18. 제17항에 있어서, 지 1,3,5 및 제7침착 속도가 40Å/초보다 큰 방법.
  19. 제1층, 제1층상에 형성된 절연체 층 및 절연체 층중에 형성된 접촉 구멍을 갖고 제1층 부분이 노출된 기제를 제공하고; 상기 접촉 구멍내에 5개 이상의 텅스텐 층을 침착시켜 적어도 거의 접촉 구멍을 충진시킴을 포함하는 전자 장치의 제조 방법.
  20. 제19항에 있어서, 상기 5개 이상의 층을 교대로 빠르고 느린 침착 속도로 침착시키는 방법.
  21. 제1층; 제2층; 및 상기 제1층과 상기 제2층 사이를 전기 접촉시키며 5개 이상의 층을 갖는 텅스텐 플러그를 포함하는 상호연결 구조물을 포함하는 전자 장치.
    ※참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950067127A 1994-12-30 1995-12-29 다층 텡스텐 침착 방법 Ceased KR960026257A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/366,529 1994-12-30
US08/366,529 US5489552A (en) 1994-12-30 1994-12-30 Multiple layer tungsten deposition process

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KR960026257A true KR960026257A (ko) 1996-07-22

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US (1) US5489552A (ko)
EP (1) EP0720211A3 (ko)
JP (1) JPH08232079A (ko)
KR (1) KR960026257A (ko)
TW (1) TW344893B (ko)

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TW344893B (en) 1998-11-11

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